Physical Fault Models and Fault Tolerance - Models in Hardware Testing - page 219

Tabl e 8. 3 Set of test vectors
detecting short #2 of Fig. 8.3 a

abcdef
100001
010001
110001
001010
000110
001110

Shorts A short between any couple of nodes in the switch-like network corre-
sponds to the creation of one or more conduction paths. Two conditions are required
to detect a short between nodes i and j : (1) activate at least one conduction path
between the output node and the i (respectively, j ) node and at least one conduction
path between the j (respectively, i ) node and the V SS node, and (2) block all other
conduction paths of the network.
When these two conditions are realized, if nodes i and j are shorted, the output
node is at logical state 0. If there is no short, the output node is at logical state
1: the potential presence of the short is observed at the output of the gate. For a
given short, usually, several test vectors enabling its detection exist. For instance,
Tab le 8.3 gives the set of six tests enabling detection of short #2 of Fig. 8.3 a . To
obtain a complete test sequence for all shorts of the switch-like network, it is first
necessary to determine in this way the set of test vectors for each of them, and then
to search for a minimal coverage enabling detection of all these shorts. If n is the
number of nodes in the network, this minimal cover presents a maximum number

of 2 vectors.

8.2.2.3 Test Sequence Generation at the Block Level

Two specific problems can be identified for testing a block interconnecting several
gates.

Controllability and Observability Assuming that a complete test sequence has
been determined for each gate of the block, we must now apply to each gate its test
sequence even if not all inputs are easily controllable and/or observable. This can be
done by using a path sensitization method based on propagation to primary outputs
of the block and consistency according to primary inputs ( Roth et al. 1978 ).

Additional Failure Modes Specific to the Block Structure We address in se-
quence the problems related to opens and shorts:

a. In addition to the opens in the gates, the block structure introduces opens in inter-
connections between gates. Such an interconnection always connects the output
of a gate to the gates of one or more control transistors of other gates. The open
of such a connection thus leads to a floating gate potential of the transistors that
are located after the open. In static operation, the leakage current is sufficient to