Models for Power-Aware Testing - Models in Hardware Testing - page 198

one scan chain segment, all other segments can have their clocks disabled. When
one scan chain segment has been completely loaded/unloaded, then the next scan
chain segment is activated.
This technique requires clock gating and the use of bypass multiplexers for
segment-wise access. It drastically reduces shift power (both average and peak) dis-
sipated in the combinational logic. It can be applied to circuits with multiple scan
chains (e.g. STUMPS architectures), even when test compression is used. It has no
impact on the test application time and the fault coverage, and requires minimal
modifications to the ATPG flow.
The main drawback of scan segmentation is that capture power remains a con-
cern that needs to be addressed. This problem can be partially solved by creating a
data dependency graph based on the circuit structure and identifying the strongly
connected components (SCC). Flip-flops in an SCC must load responses at the
same time to avoid capture violations. This way, capture power can be minimized
( Rosinger et al. 2004 ).
Low power scan partitioning has been shown to be feasible on commercial de-
signs such as the CELL processor ( Zoellin et al. 2006 ).

7.5.2 Staggered Clocking

Various staggered clock schemes can be used to reduce test power consumption
( Sankaralingam and Touba 2003 ; Lee et al. 2000 ; Huang and Lee 2001 ). Staggering
the clock during shift or capture achieves power savings without significantly af-
fecting test application time. Staggering can be achieved by ensuring that the clocks
to different scan flip-flops (or chains) have different duty cycles or different phases,
thereby reducing the number of simultaneous transitions. The biggest challenge to
these techniques is its implications on the clock generation, which is a sensitive
aspect of chip design. In this section, we describe a staggering clocking scheme
proposed in Bonhomme et al. ( 2001 ) that can achieve significant power reduction
with a very low impact and cost on the clock generation.

7.5.2.1 Basic Principle

The technique proposed in Bonhomme et al. ( 2001 ) is based on reducing the oper-
ating frequency of the scan cells during scan shifting without modifying the total
test time. For this purpose, a clock whose speed is half of the normal (functional)
clock speed is used to activate one half of the scan cells (referred to as “Scan Cells
A” i n F i g . 7.11 ) during one clock cycle of the scan operation. During the next clock
cycle, the second half of the scan cells (referred to as “Scan Cells B”) is activated
by another clock whose speed is also half of the normal speed. The two clocks are
synchronous with the system clock and have the same period during shift operation
except that they are shifted in time. During capture operation, the two clocks operate