Models for Power-Aware Testing - Models in Hardware Testing - page 199

Fig. 7.11 Staggered clocking

scheme

Combinational Logic

ComOut

CLK/2 s CLK/2

Scan Cells A Scan Cells B

SI

1
0

SO

SE

ATE

SE

Scan
Cells
A

“CLK/2”

Clock
Tree

Test
Clock
Module

CLK

CUT

Scan
Cells
B

“CLK/2 σ ”

Clock
Tree

ComOut

ATE

Fig. 7.12 The complete structure

as the system clock. The serial outputs of the two groups of scan cells are connected
to a multiplexer that drives either the content of Scan Cells A or the content of Scan
Cells B to the ATE during scan operations. As values coming from the two groups
of scan cells must be scanned out alternatively, the multiplexer has to switch at each
clock cycle of the scan operations.
With such a clock scheme, only half of the scan cells may toggle at each clock
cycle (despite the fact that a shift operation is performed at each clock cycle of
the whole scan process). Therefore, the use of this scheme lowers the transition
density in the combinational logic (logic power), the scan chain (scan power) and the
clock tree feeding the scan chain (clock power) during shift operation. Both average
power consumption and peak power consumption are significantly minimized in all
of these structures. Moreover, the total energy consumption is also reduced as the
test length with the staggering clocking scheme is exactly the same as the test length
with a conventional scan design to reach the same stuck-at fault coverage.

7.5.2.2 Design of the Staggered Clock Scheme

The complete low power scan structure is depicted in Fig. 7.12 . This structure is
first composed by a test clock module which provides test clock signals CLK/2 and
CLK=2¢ from the system clock CLK used in the normal mode. Signal SE allows to