Models for Power-Aware Testing - Models in Hardware Testing - page 197

to the combinational logic. Obviously, this technique is very effective in reducing
shift power. However, it induces design overheads (area and functional timing) and
timing closure issues related to the scan enable signal.
Alternative techniques such as first-level power supply gating have emerged that
do not require modifications of the scan cells. Power switches are added between
the power supply and the first level of combinational logic. Such a technique also
helps in reducing leakage power consumption.

7.5.1.2 Scan Cell Reordering

Shift power can also be reduced by changing the order of the scan cells in each
scan chain of a design. Of course, changing the order of the scan cells in the scan
chains implies a change of the bit order in each test vector to preserve the initial
fault coverage. Finding the best (less power consuming) order of scan cells in the
scan chains is a complex problem and polynomial-time approximation algorithms
have therefore to be used for large designs.
Scan cell ordering has many advantages as it does not require additional hard-
ware, the fault coverage and test time are left unchanged, the impact on the design
flow is very low, and significant reduction in test power can be obtained. How-
ever, power-driven stitching of the scan cells may result in longer interconnections
between the scan cells and congestion issues during scan routing. To solve these
problems, physical design constraints can be included in the reordering algorithm
( Bonhomme et al. 2003 ).

7.5.1.3 Logic Insertion in Scan Chain

This technique consists in inserting logic elements (XOR gates) between the scan
cells so as to minimize the occurrence of transitions in the scan chains (and hence
in the combinational logic) during shift operations. Adding logic elements in the
scan chains transforms the logic values that need to be shifted in. By doing this
intelligently, it is possible to transform the scan vectors so that they contain fewer
transitions. Although efficient to reduce shift power (in both combinational logic and
scan path), the computational demand of this solution increases with the number of
scan cells and the pattern count. Moreover, the scan chains are built based on the
available test set, so that adding top-off patterns can be a problem.

7.5.1.4 Scan Chain Segmentation

The basic concept in scan segmentation is to divide a given chain into two (or N)
scan chain segments, and then activating one segment at a time when loading and
unloading test data ( Whetsel 2000 ; Saxena et al. 2001 ). During the shift in/out of