Models for Power-Aware Testing - Models in Hardware Testing - page 196

In order to determine whether a disadvantageous transformation will be ac-
tually accepted or not, we use a number denoted p which is randomly chosen
between 0 and 1 with a uniform distribution. This number is then compared
with P find better solution that represents the probability to find a better solution and
which is calculated from the Gibbs-Boltzmann distribution. The temperature in the
Gibbs-Boltzmann distribution is a control parameter that fixes the number of dis-
advantageous solutions that can be accepted. The temperature takes a high value at
the beginning of the annealing process, and decreases after each acceptance of a lo-
cal solution. When the temperature is low enough, only advantageous solutions are
accepted.
The above simulated annealing algorithm proposed to find a “good” LFSR seed
has been validated experimentally and results can be found in Girard et al. ( 1999 ) .
These results show that energy during BIST can be significantly reduced with no
loss of fault coverage. On the other hand, average power consumption can not be
minimized with such approach. Only issues related to battery lifetime can hence be
addressed in this case.

7.5 Design for Power-Aware Testing

Dedicated Design-For-Test (DFT) solutions offer a structured and configurable
means to reduce test power consumption. In this section, we first give an overview
of the various low-power DFT solutions proposed so far. Next, we present one of
these solutions based on staggered clocking.

7.5.1 Overview of Power-Aware DFT Solutions

Low power DFT has been an active research area for more than one decade. Nu-
merous solutions have been proposed so far and some of them are surveyed below.
A more complete presentation of low power DFT solutions can be found in Girard
et al. ( 2007 ).

7.5.1.1 Gated Scan Cells

The combinational logic toggling that happens during scan shifting can be elimi-
nated (or reduced) by incorporating a blocking circuitry at all (or some) outputs of
the scan flip-flops. Although there exists various ways of implementing the block-
ing logic (muxes, transmission gates, etc.), a typical solution consists in adding a
NOR gate as a blocking element, with the scan enable of the flip-flop also serv-
ing as blocking enable signal ( Gerstend orfer and Wunderlich 1999 ) . During scan
shifting, the NOR gate can hence prevent data in the scan cells from propagating