Hardware Reference
In-Depth Information
where a list of FFMs described in terms of FPs defines a set of conditions able
to detect the target faulty behaviors to be later combined into a resulting march
test, is becoming a bottleneck. Due to the increased number of FPs to consider, the
complexity of the resulting test algorithms is drastically increasing. Increased com-
In several situations such a significant overhead is not justified with respect to the
very marginal improvement in defect coverage they provide.
This makes it mandatory introducing a stronger link between functional test and
physical defects, thus moving from
fault-based test approaches
to
defect-based test
approaches
.
Defect-based testing typically aims at targeting the following questions:
What can go wrong with this design? How would the design's behavior change if this hap-
pen, and how can that be measured
?
(
Aitken et al.
2003
)
Several publications already proved that, working with device level memory models,
the set of realistic fault models for a specific memory architecture and technol-
ogy can be drastically reduced. Moreover, resorting to the detailed information
about memory architecture and technology, optimized test algorithms can be imple-
mented, drastically reducing the overall test time and complexity while guaranteeing
While defect-based test represents a key element to reduce test cost, it presents
the main drawback that test algorithms should be deeply customized to the target
memory technology and architecture. Defect-based testing for memory concentrates
on defect analysis of key parts of the layout and the development of test patterns that
will test for likely failures. This is completely in contrast with the architecture and
technology independent form of traditional march tests. In order to be effectively
applicable in an industrial scenario, defect-based memory testing requires a strong
investment in automating all steps, from defect analysis and simulation, to realistic
fault models extraction, and to test generation. Few publications addressed these
problems so far
Cheng et al.
(
2003
)
,
Al-Ars et al.
(
2005
), and
Di Carlo et al.
(
2008
)
with all the proposed solutions still far from being applicable in real scenarios. Such
a big challenge will most likely be leading several researchers in the field of defect-
based memory testing in next years.
6.7
Summary
We would like to conclude this chapter with a thought about the future of memory
modeling and testing. The first era of memories lasted roughly 10 years, the second
one 20 years. We are now around 30 years of semiconductor memories. What's
next? Which technologies will allow us to store the hundreds of terabytes we are
going to need tomorrow? How shall we model and test these monster devices?
