Hardware Reference
In-Depth Information
*
.r
1
w
0
r
0
w
0
r
0
/
*
.r
0
w
1
r
1
w
1
r
1
/
m
.r
0
/
March tests are a preferred method for RAM testing either by means of external
testers or through built in self test (BIST) solutions. Their linear complexity, regu-
larity, and symmetry are the reason for this preference. However, tests for NPSFs
(see Section
6.4.5
)
cannot be performed by march tests (
Mazumder et al.
1996
)
,
since the base cell needs to be addressed differently from the cells in the deleted
neighbor, thus requiring test algorithms with higher complexity difficult to imple-
ment in embedded test environments.
6.5.1
Generation of March Tests
The generation of a march test begins with the analysis of a set of target FPs used
to identify so-called detection conditions providing the minimum requirements a
march test has to achieve in order to detect the target faulty behaviors. Detection
conditions can be then combined together to provide a complete march test.
As an example, starting with the following FP <0;
w
1
=0=
> modeling a TF
1
transition fault, it is easy to derive that any march test containing the following
conditions:
m
.:::
w
0
:::/
m
.:::
w
1
:::/
m
.:::r
1
:::/, is able to detect the target
faulty behavior. Multiple detection conditions needed to detect a number of different
FPs have to be combined together to generate a single march test to fully test the
memory for all targeted faulty behaviors.
The automatic generation of march test is a deeply studied and analyzed problem
and several generation algorithms are available in the literature:
Smit et al.
(
1994
)
,
Zarrineh et al.
(
1998
),
Wu et al.
(
2000
),
Zarrineh et al.
(
2001
),
Cheng et al.
(
2002
)
,
Benso et al.
(
2002
)
,
Al-Harabi et al.
(
2003
),
Niggemeyer et al.
(
2004
),
Benso
6.6
From Fault-Based to Defect-Based Memory Testing: Trends
and Challenges
Functional tests and functional fault models proved to be very helpful in generating
functional test algorithms independent of the target technology and able to guarantee
high fault coverage and therefore high quality in memory products. Unfortunately,
as technology continuously scales down, and we fully enter the VDSM era, the
sensitivity of memories to physical defects is strongly increasing. This turns into
the continuous identification and definition of new dynamic faulty behaviors (see
