Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 4

1.2.1.1 Full Open Defects in Interconnect Lines

In this subsection, we first review the classical model for full opens in interconnect
lines capacitively coupled with neighboring lines. As traditionally considered, tun-
neling currents are assumed negligible. Next, thin open defects are described, and
finally interconnect full open defects with gate leakage are modeled.

Full Open Defect Modeling in the Interconnect Paths

An interconnect line with a full open is disconnected from its driver and becomes
electrically floating. This line may, in turn, drive one (or more) transistor pair(s).
An illustrative example is shown in Fig. 1.3 , where the interconnect line is driving
an inverter. The floating line voltage .V FL / is determined by (a) the surrounding
circuitry, (b) the transistor capacitances of the driven gates, and (c) the initial trapped
charge ( Konuk 1997 ; Champac and Zenteno 2000 ; Arumı et al. 2005 ), as reviewed
next.

a. Neighboring interconnect lines routed close to the floating line add parasitic cou-
pling capacitances (C N1 ,C N2 ,C N3 , :::C Nm in Fig. 1.3 ) . There are also parasitic
capacitances to the ground .C SUBS / and to the power plane .C WELL /. Without
loss of generality, an n-well CMOS process is considered in Fig. 1.3 . Thevalue
of these capacitances depends on the dielectric filling the space, the distance be-
tween lines and their physical dimensions.
b. Another set of parasitic capacitances influencing the interconnect line is made
up of the parasitic capacitances of the transistors driven by the floating line.

These capacitances consist of gate drain C gd ,gatesource C gs and gate bulk

C gb capacitances from both the pMOS and nMOS transistors of the down-
stream gate(s). The exact value of these transistor capacitances varies with the
conduction state of the transistors.

C gs(p)

C gb(p)

N 1 N 3 N m

C N1 C N3 C Nm C WELL

C gd(p)

I N

FL

Driving
gate

OUT

C gd(n)

C N2 C SUBS

C gb(n)

N 2

C gs(n)

Fig. 1.3 Electrical model for an interconnect full open