Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 5

c. The third factor influencing the floating line voltage is the trapped charge
accumulated in the floating structure during the fabrication process. The trapped
charge is an unknown, difficult-to predict parameter. In the work by Johnson
( 1994 ), measurements of the trapped charge were made on test structures con-
sisting of floating-gate transistors with different polysilicon length extensions.
These measurements always showed a positive charge on the floating polysilicon,
generating voltages ranging from 0.1 to 2.3 V.

According to the charge conservation law, once the initial charge is trapped in the
circuit, the total charge does not change and is redistributed among the connected
capacitors. Therefore, for the example in Fig. 1.3 , Eq. 1.1 must be satisfied:

X

iDm

Q Ni C Q VDD C Q GND C Q M D Q o (1.1)

iD1

The sum of Q Ni represents all the charges from the coupled neighbors, Q VDD is the

charge from capacitances tied to the power rail C WELL C C gb.p/ C C gs.p/ ,Q GND

is the charge from capacitances tied to the ground rail C SUBS C C gb.n/ C C gs.n/ ,

Q M is the charge related to the Miller capacitances C gd.n/ C C gd.p/ and Q o is
the trapped charged accumulated during the fabrication process. Using the well-
known expression relating the charge and the voltage across the capacitor terminals
(Eq. 1.2 ) andEq. 1.1 , the expression in terms of V FL and V OUT reported in Eq. 1.3 is
obtained:

Q D C V (1.2)

.V FL V DD /.C NL1 C C VDD / C V FL .C NL0 C C GND /
C .V FL V OUT / C M D Q o (1.3)

C NL1 is the capacitance from all the neighbors set to logic 1 and C NL0 the capaci-
tance from all neighbors set to logic 0. C NL1 and C NL0 are logic pattern dependent,
since for every test pattern, a different state is set in the neighboring lines. In general,
the drivers managing the neighboring lines are strong, hence these capacitances can
be considered to be tied to V DD or GND in steady state. In this way, Eq. 1.3 can be
rearranged as follows:

.C UP C C DOWN C C M / V FL C UP V DD C M V OUT D Q o (1.4)

where C UP is the sum of all the parasitic capacitances tied to V DD .C NL1 C C VDD /
and C DOWN is the sum of all the parasitic capacitances tied to GND .C N0 C C GND /.
For a wide range of input voltages .V FL /, the output voltage .V OUT / is set to
digital values (GND and V DD ). In these situations, C M becomes part of C UP or
C DOWN . Hence, V FL can be isolated in Eq. 1.4 , resulting in the simplified expres-
sion in Eq. 1.5 :