Hardware Reference
In-Depth Information
Depending on its resistance an open can also be classified into two different groups
based on its electrical model:
Full (or strong) open:
The lack of conductive material causes a discontinuity,
thus eliminating the electrical connection between the two end points of the
defect site.
Resistive (or weak) open:
The discontinuity does not result in a complete electri-
cal disconnection adding a finite resistance.
Other classifications based on the physical cause of the defect have also been used
in the literature. What is considered in these categorizations are the basic operations
in IC fabrication where open defects are more likely to appear: photolithography,
mechanical planarization processes and chemical problems in contacts and vias.
1.2
Open Defect Models
Extensive work has been conducted to model opens and characterize the behavior
of CMOS circuits with open defects. The first works on intra-gate opens appeared
in the late 1970s. Stuck-open faults and the “two vector detection” of the defect
were published (
Wadsack 1978
). Pioneering work on modeling and electrical anal-
ysis of gates with a single floating transistor gate were performed in the late 1980s
(
Renovell and Cambon
1986
,
1992
). Models and CMOS circuits with interconnect
opens were electrically characterized later during the 1990s when the interconnect
architecture of VLSI circuits started to become more prone to interconnect opens
than intra-gate opens. The number of publications on interconnect opens has in-
creased significantly since then.
In this section, the evolution of modeling and electrical characterization of cir-
cuits with opens is reviewed, presenting some key developments in the field. The
section has been divided into two subsections based on open location, i.e., intercon-
nect and intra-gate opens.
1.2.1
Interconnect Open Defects
The physical explanation of interconnect opens can be either a metal or polysilicon
crack/void or a defective contact/via. These open defects result in gate input pairs
being partially or totally disconnected from their drivers. Although opens may ap-
pear inside a logic module in CMOS technologies, the most likely place to appear
is in an interconnect line (
Xue et al.
1994
). For this reason, special attention is paid
to interconnect opens.
A review of interconnect open defects is provided next, following the classifica-
tion according to defect resistance, i.e.
full
and
resistive
opens.
