Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 2

a b

Fig. 1.1 Interconnect open defect photographs for a copper interconnect technology (Courtesy of
NXP Semiconductors). ( a ) Defect in metal and ( b ) defect in via

a b

Interconnect open

Transistor network
open

Driver Load

Bulk open

Single floating gate

Fig. 1.2 Open defect classification based on location. ( a ) Interconnect and ( b ) intra-gate

An open defect can be classed according to its location (see Fig. 1.2 ) , as inter-
connect and intra-gate opens, with the following subtypes:
Interconnect opens:
Metal/Polysilicon open: This break is located on metal or in polysilicon tracks.
Via open: It is located in via that connects two metal tracks of different metal
layers.
Contact open: It is located in a contact between silicon and a metal track, or
polysilicon and a metal track.
Intra-gate opens:
Transistor network open: It appears inside a logic gate and affects the connection
between the drain/source of one or more transistors.
Bulk open: In bulk CMOS technologies, the defect breaks or weakens the con-
nection between the bulk of an nMOS transistor and GND, or the bulk of a pMOS
transistor and V DD .
Single/Multiple floating gate(s): It disconnects a single or multiple transistor
gate(s) from its (their) driver.