Hardware Reference
In-Depth Information
The outcome of production diagnosis is used to infer yield limiters rather than
performing physical failure analysis. Again, a diagnosis algorithm should provide a
set of suspect signals for each failing device and both structural and functional data
has to be generated for each candidate.
5.3
Fault Model Independence
Diagnostic fault models describe the defect candidates formally, and have structural
and functional aspects. The structural aspects provide information on the locations
of the defects in the circuit, and the functional aspects relate to the erroneous behav-
ior. The conditional line flip (CLF) calculus is able to reflect these basic properties,
and enables defect classification.
5.3.1
The Conditional Line Flip (CLF) Calculus
The CLF calculus is based on some observations described below. For the sake of
simplicity, we will discuss the observations for the defects on gate level. The same
arguments also hold for any gate-internal defects.
Each detectable defect disturbs the electrical behavior of one or more lines close
to the defect site. The lines, which are influenced by the defect in this way, are called
victims. A victim, like any signal line, has a driving gate and one or more receiving
gates. In the general case, both drivers and receivers are influenced by the electrical
conditions of a victim. This influence can also cause the neighborhood of this line
to operate in a faulty way.
The receivers evaluate a degenerated voltage level at the victim line. Due to vari-
ations in the threshold voltages of the transistors in these gates, they may even
come to different interpretations of the input voltage. While one receiver consid-
ers a certain voltage level being logic 1, another receiver of the same victim line
reads logic 0. This is known as the Byzantine effect, and it is only one example of
logically inconsistent operations caused by a defect (see Chapter
2
).
Figure
5.1
shows an example of how a bridging defect influences two lines a
and b. The logic behavior in this area is inconsistent, as gates x and y interpret the
voltage level of line a differently. Outside the area of influence, the logic behavior
is consistent again.
The proper operation of the victim's driving gate may be influenced too, by the
defect. Here, a high current drain of the victim line may cause the driver to operate
outside the specified limits and change its behavior.
The electrical influence of a defect can also propagate over multiple gates. If a
receiving gate uses pass transistor logic, it might not produce a proper logic signal
when connected to a degraded input signal. If a defect causes a short between two
lines, it may compromise the power grid in the surrounding area. This is known
as power droop and can cause multiple gates to fail (
Tirumurti et al.
2004
;
Polian
et al.
2006
).
