Hardware Reference
In-Depth Information
reduced by an efficient ranking of possible defect locations and by investigating the
functional behavior of the defect itself.
Consider for instance a defect which sometimes drives an internal signal line to a
faulty value. A stuck-at fault on this line can explain all erroneous responses of this
circuit. However, the stuck-at fault might predict additional errors not observed in
the device under test. These kinds of mispredictions can be used to record the set of
test patterns for which the defect was inactive. This functional information can be
correlated to the values of the neighboring line for each test pattern. If a strong cor-
relation with another signal line can be found, the actual defect can be located close
to both signals, the faulty one and the aggressing one. It is reasonable to investigate
the areas first, where both signal lines are close together. Also, the line segments or
vias of open defects can be determined precisely, if the states of the coupling sig-
nals are taken into account (
Liu et al.
2007
), and bridges can be characterized more
precisely, if the Byzantine effect is considered (
Khursheed et al.
2008
)
.
Therefore, a candidate for PFA should be described with both the internal signal
lines from where the erroneous output originates and the functional behavior or
activation conditions of the victims. Combined with the layout of the design, this
leads to accurate spatial coordinates for examination.
5.2.2
Yield Management
Yield ramp is part of the step from the prototyping phase into volume production
and opens the next major application field of logic diagnosis. The goal in this phase
is the optimization of the manufacturing process to achieve higher yield, to reduce
the fabrication cost per functioning chip and to increase the product quality. The
obtained diagnosis results are combined by using data-mining techniques to extract
layout structures or features that fail in a significant number of chips and thus impact
the yield. Based on this information, layout and process parameters are optimized.
The requirements for logic diagnosis on production fail data are different. While
there is a huge amount of data to be analyzed for each production line, the fail data
for a single device is rather limited. The limitation in response data has multiple
reasons. The most obvious one is the test response compaction used to reduce the
bandwidth needed between tester and device, and diagnosis has to be performed
on compacted response data. Moreover, as tester memory is limited and the test
time used on failing devices is usually kept as short as possible, only the first erro-
neous signatures are recorded. Another limitation stems from the used production
test patterns. These pattern sets are kept small to reduce test time. Hence, each pat-
tern excites many faults at the same time making it hard for diagnosis algorithms to
distinguish between possible candidates (
Chen et al.
2006
).
Despite all these limitations of the input data for diagnosis, the algorithms must
provide good predictions with a limited amount of computing power. With thou-
sands of fail data sets coming in each minute during production, any increase in
the analysis time of one data set has a great impact on the overall performance
requirements.
