Hardware Reference
In-Depth Information
Instead of searching in a predefined set of fault candidates, diagnosis algorithms
have to locate defective internal signals directly and identify the nature of the defect.
To describe these defects, a generalized fault modeling calculus is needed. The re-
quirements for this calculus are threefold. It must be able to express all the possible
defective behaviors to a large extent, and the description of a defect must provide
enough detail for the targeted failure analysis. Furthermore, the description of a
defect should be as simple as possible in order to allow a ranking of the suspects
corresponding to the complexity of the explanation.
Compared to the classical fault models, the calculus presented below does not
impose any restrictions on the nature of a defect. Instead, the diagnosis method may
restrict the set of defects to consider a certain class by additional constraints. Very
common assumptions are for instance the deterministic behavior of a defect or that
there is only one defect location in the device.
First, we will discuss the major application fields of logic diagnosis to describe
the available input data and the formal requirements for representing diagnosis
results. Section
5.3
will discuss the conditional line flip (CLF) calculus, provide
examples and compare it to other general fault modeling approaches. Section
5.4
presents an application of the CLF calculus to logic diagnosis in order to locate
defective regions in a circuit without any fault assumptions.
5.2
Applications
5.2.1
Prototyping and Characterization
Prototypes of a new design or a new technology may not work properly due to un-
known effects. Systematic and random variations in modern technologies require
the layout as well as the production process being fine-tuned to achieve acceptable
yield. The failing prototypes must be thoroughly analyzed for determining the opti-
mization tasks.
A typical case of using logic diagnosis in this environment is the preparation for
physical failure analysis (PFA). PFA with its de-processing and imaging techniques
is costly, time intensive and in most cases destructive. Before PFA, the erroneous
behavior is analyzed to derive possible locations of a defect. As this analysis is done
only for rather few cases, extensive fail data can be collected for logic diagnosis.
The available time permits the bypassing of any on-chip test compression logic
and the application of large diagnostic pattern sets. Logic diagnosis, diagnostic pat-
tern generation and pattern application can even be coupled to diagnose a defect
adaptively. Based on the suspicious region determined by diagnosing responses to
a standard pattern set, specially generated diagnostic patterns are generated and ap-
plied to improve diagnostic resolution.
The performance of a diagnosis algorithm in this application is measured by
the area that has to be examined physically until the defect is found. This area is
