Generalized Fault Modeling for Logic Diagnosis - Models in Hardware Testing - page 131

Debug is the time-consuming task of identifying faulty modules and structures
within the design. While some methods of formal verification are constructive and
able to find the cause of malfunctions, simulation and emulation usually require
additional efforts for fault location. As design complexity increases, verification is
turning into a critical bottleneck in the development process. Estimates today are
that more than 70% of the total design time is on verification ( Chen 2003 ; Klein and
Piekarz 2005 ). Despite the efforts spent by academia and industry on developing
functional verification tools, logical and functional flaws remain the main cause of
today's design respins.
Diagnosis is the process of locating faults in a physical chip at various levels
down to real physical defects. Numerous parasitic and timing effects may show
up in the first silicon ( Roy et al. 2006 ), identifying them is part of silicon debug.
With growing circuit complexity and shrinking geometries, the actual behavior of
the silicon is hard to model ( Krstic et al. 2003 ; Henderson and Soden 1997 ; Lavo
et al. 1998 ) , and cannot always be predicted and simulated ( McPherson 2006 ).
In volume diagnosis , test data of a large number of failing chips are recorded and
analyzed to find yield-limiting systematic defects and design issues. Diagnostic data
from a single chip is not sufficient since systematic problems need to be differen-
tiated from sporadic random defects. The extracted knowledge is used to support
yield ramping and yield learning in advanced process technologies by improving
design for manufacturability ( Hora et al. 2002 ).
Precision diagnosis is performed on a small selected set of chips like first silicon
or representatives for systematic defects determined by volume diagnosis to find the
exact defect mechanisms in the individual chips. The constraints on computing time
are reduced but high diagnostic resolution has to be provided to guide the physical
inspection accurately.
Diagnosis is more related to defects and debug is closer to design errors, i. e.
errors of the designer. However, both diagnosis and debug share many common
objectives like achieving high diagnostic resolutions ( Riley et al. 2006 ; Arnaout
et al. 2006 ) . Especially fault model independent approaches are suitable for both of
these tasks.
For recent process technologies, defect mechanisms are increasingly complex,
and continuous efforts are made to model these defects by using sophisticated fault
models. Many debug and diagnosis algorithms are designed for specific fault mod-
els and reach more and more their limits. Choosing a fault model like the stuck-at
fault model defines the set of all faults to be considered. With this set at hand, the
algorithms select some candidates, whose behavior matches the observed responses.
This works well, if the behavior of the defects closely resembles the behavior of the
modeled faults. However in the current nanometer technology, there are numerous
interactions between physical features in real silicon. Many of them have already
been described with specialized fault models in the previous chapters; some of them
are not well understood yet or too complex for useful modeling. This situation poses
the most severe challenge for recent diagnosis algorithms. There is no single fault
model anymore, that can describe all the possible defects, and there is no well de-
fined set of faults anymore to choose from.