Hardware Reference
In-Depth Information
Chapter 5
Generalized Fault Modeling for Logic Diagnosis
Hans-Joachim Wunderlich and Stefan Holst
Abstract
To cope with the numerous defect mechanisms in nanoelectronic
technology, more and more complex fault models have been introduced. Each
model comes with its own properties and algorithms for test generation and logic
diagnosis. In diagnosis, however, the defect mechanisms of a failing device are
not known in advance, and algorithms that assume a specific fault model may fail.
Therefore, diagnosis techniques have been proposed that relax fault assumptions
or even work without any fault model. In this chapter, we establish a generalized
fault modeling technique and notation. Based on this notation, we describe and
classify existing models and investigate the properties of a fault model independent
diagnosis technique.
Keywords
Logic diagnosis
Fault models
5.1
Introduction
Diagnosis is essential in modern chip production to increase yield, and debug con-
stitutes a major part in the pre-silicon development process. Locating the structural
problems by observing erroneous behavior is essential for debug and preparing
physical analysis of prototypes and field-returns as well as for data-mining pro-
duction fail data.
Traditionally, design, verification and diagnosis of microelectronic circuits have
been viewed as separate tasks with individual challenges and techniques. However,
in recent years more and more attention has been paid to the interaction of individual
design steps in verification, diagnosis of prototypes, and field return analysis. These
tasks support quality control and improvement during the complete lifecycle of the
system by tackling faults occurring during design, manufacturing and operation.
)andS.Holst
Institut fur Technische Informatik, Universitat Stuttgart, Pfaffenwaldring 47, D-70569
Stuttgart, Germany
e-mail:
wu@informatik.uni-stuttgart.de
H.-J. Wunderlich (
