Hardware Reference
In-Depth Information
bridging faults, scalable fault simulation and ATPG methods are presented. Their
efficiency is based on representing non-trivial electrical behavior by discrete ob-
jects which can be handled by fast algorithms. This allows to leverage speed-up
techniques developed in the past for stuck-at faults while not compromising ac-
curacy. SPICE-level precision becomes available for moderately-sized academic
benchmark and even multi-million gate industrial circuits.
The utility of algorithms based on the resistive bridging fault model is not re-
stricted to traditional roles of fault simulation and ATPG. We have mentioned above
that they can help making informed choices when selecting the right strategy for
testing under non-nominal conditions. A further application of the resistive bridg-
ing fault framework has helped to design a built-in self test (BIST) solution with
useful to validate the performance of any test method optimized to detect stuck-at
faults for other defect classes.
Although the results reported in this chapter are extensive, there remain a number
of research challenges. One such challenge is the creation of adequate electrical
models for both resistive bridging and resistive open faults in future technologies.
One can generally assume that dynamic effects will play a dominant role in defect
behavior. Complex interactions with other circuit elements, e.g., capacitive-coupled
aggressor lines, may require more elaborate electrical modeling. Fault simulation
and ATPG will probably somewhat resemble methods used today for delay faults.
See Chapter
3
for an introduction to delay faults.
A further open question is the impact of statistical process variations on the qual-
ity of the obtained data. For the model presented in this chapter, the impact of
process variations is expected to be limited, due to the following reason. Process
variations will lead to different technology parameter and thus different critical re-
sistances in different manufactured instances of the same circuit. As a consequence,
C-ADI and G-ADI of a fault may differ throughout the manufactured circuit popu-
lation and also may deviate from the intervals predicted without considering process
variations. However, fault simulation and ATPG are concerned with the fault cover-
age, i.e., the
ratio
between C-ADI and G-ADI (weighted by ยก) rather than the exact
boundaries of the intervals. Since C-ADI and G-ADI are computed from critical
resistances, a larger C-ADI will typically be matched by a larger G-ADI, and the
cumulative effect on the fault coverage will be reduced. This argumentation may
not be valid for dynamic effects of resistive faults where fault detection generally
depends on variations of all circuit components, not only of logic gates at the bridge
site. Novel approaches to fault simulation and ATPG, possibly incorporating statis-
Acknowledgments
We are thankful to Dr. Piet Engelke of University of Freiburg for his
contributions. The work was partially funded by the German Research Council (grant Be
1176/14-1).
