Hardware Reference
In-Depth Information
∩
G
nom
∫
r
(
r
)
dr
∫
G
nom
r
(
r
)
dr
C
nn
FC
nn
=
100%
⋅
.
∫
(
C
nom
∪
C
nn
)
∩
G
nom
r
(
r
)
dr
FC
comb
=
100%
⋅
.
∫
G
nom
r
(
r
)
dr
∫
([0,∞]\
G
nom
)∩
C
nn
r
(
r
)
dr
∫
([0,∞]\
G
nom
)
r
(
r
)
dr
FC
flaw
=
100%
⋅
.
Fig. 4.6
Definitions and Venn diagrams of non-nominal coverage, combined fault coverage and
flaw coverage
the fault coverage definitions. Diagonal lines and vertical lines refer to the numerator
and the denominator of the formulae, respectively.
crease the coverage of hard defects even if performance degradation introduced by
lowering V
DD
is compensated by excluding some patterns from the test set. The cov-
erage increase by low-temperature testing is limited. Given that low-voltage testing
is associated with less equipment cost than low-temperature testing, it appears to
be more efficient to detect hard defects. The detection of flaws is maximized when
voltage and temperature are lowered simultaneously. It must be kept in mind that
this conclusion may not be valid for defect classes other than resistive bridging
faults.
4.6
Summary
Resistive faults are an important defect class in nanoscale CMOS. Traditional test
methods based on the stuck-at fault model detect a significant fraction of resistive
faults by incidence, yet this may not be sufficient to ensure an adequate coverage of
such faults. Targeting resistive faults has been considered prohibitively complex in
the past, mainly due to difficulties associated with modeling an infinite number of
resistances a defect could have.
The work presented in this chapter demonstrates the feasibility of handling re-
sistive faults directly. For an important sub-class of resistive faults, the resistive
