Fault Modeling for Simulation and ATPG - Models in Hardware Testing - page 125

site and gate-level simulation. The fault-site analysis establishes the relationship be-
tween the defect resistance and the additional delay induced by the defect. It must
take into account capacitive couplings between the bridged lines (crosstalk). The
gate-level simulation determines the ranges of defect-induced delays for which the
circuit will fail. Combining this information, one could derive C-ADI as the range
of bridge resistances for which the circuit timing is violated.

4.5.4 Non-nominal Conditions

The detection capabilities of a test set with respect to some classes of defects
are enhanced if test application is performed under non-nominal conditions such
as lowered power supply voltage .V DD / ( Hao 1993 ) or ambient temperature
.T / ( Needham 1998 ) . Resistive bridging faults constitute one such defect class
( Liao 1996 ; Renovell 1996 ). Testing under non-nominal conditions is also effective
in identifying flaws , i.e., defects which are present in the circuit yet are “too weak”
to cause a failure. The flaws may deteriorate over time due to various aging mech-
anisms and lead to circuit failures during its life time. Detecting flaws is the main
reason for performing costly stress tests such as burn-in ( Pecht 1998 ). A further
interest in dependence of defect detection capability from voltage and temperature
derives from the increased popularity of circuits operating at multiple V DD levels to
reduce their power consumption ( Khursheed 2008 ) .
Using the framework introduced earlier in this chapter, one could define C-ADI
and G-ADI under both nominal and non-nominal conditions. Both V DD and T can be
taken into account when critical resistances are calculated. Performing fault simula-
tion and ATPG introduced above, C-ADI and G-ADI under nominal conditions are
determined (we refer to them as C nom and G nom , respectively). Repeating the same
procedures using critical resistances calculated using lower V DD and/or T yields
C-ADI and G-ADI under non-nominal conditions, called C nn and G nn . Note that

C nom G nn hold. C nom is often (though not always) included

in C nn . Flaws are defects which cannot be detected under nominal conditions, i.e.,
defects with resistance R sh 2 Œ0; 1 n G nom . We refer to defects with R sh 2 G nom as
hard defects .
The detection capability under non-nominal conditions is measured using three
fault coverage metrics ( Engelk 2008 ) shown in Fig. 4.6 (all definitions are again
with respect to one fault f , which is omitted for brevity). The non-nominal fault
coverage FC nn corresponds to the probability that non-nominal testing will detect
a hard defect. The combined fault coverage FC comb assumes two test applications:
one under nominal and one under non-nominal conditions. A defect is considered
detected if it has been detected during at least one of the test applications (i.e., it
is included in either C nom or C nn ). FC nn and FC comb both explicitly do not count
flaw detections by restricting the integral in the numerator to G nom . Flaw coverage
FC flaw calculates the probability to detect a flaw, i.e., the likelihood that a defect in
.Œ0; 1 n G nom / is covered by C nn . The figure also shows Venn diagrams illustrating

G nom and C nn