Hardware Reference
In-Depth Information
can be obtained from several topics, topic chapters and review articles that cover de-
lay fault testing in greater detail (
Krstic et al.
1998
;
Pomeranz et al.
1998
;
Bushnell
et al.
2000
;
Jha et al.
2003
;
Wang et al.
2008
a).
References
Abraham J, Goel U, Kumar A (Apr 2006) Multi-cycle sensitizatizable transition delay faults. Pro-
ceedings of VLSI test symposium, pp 308-313
Abramovici M, Breuer M, Friedman AD (1990) Digital systems testing and testable design. IEEE
Press
Ahmed N, Tehranipoor M, Ravikumar CP, Butler KM (May 2007) Local at-speed scan enable
generation for transition fault testing using low-cost testers. IEEE Trans Comput-Aided Des
Integrat Circuits Sys 26:896-906
Barzilai Z, Rosen B (Sep 1983) Comparison of AC self-testing procedures. Proceedings of inter-
national test conference, pp 89-94
Benware B, Liu C, Van Slyke J, Krishnamurthy P, Madge R, Keim M, Kassab M, Rajski J (Oct
2004) Affordable and effective screening of delay defects in ASICS using the inline resistance
fault model. Proceedings of international test conference, pp 1285-1294
Brand D, Iyengar VS (Oct 1994) Identification of redundant delay faults. IEEE Trans Comput-
Aided Des Integrat Circuits Sys 13:553-565
Breuer MA (Oct 197) The effects of races, delays, and delay faults on test generation. IEEE Trans
Comput C-23:1078-1092
Bushnell M, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed
signal circuits. Frontiers in electronic testing volume 17. Springer
Cai Y, Schmitz MT, Al-Hashimi BM, Reddy SM (Jan 2007) Workload-ahead-driven online energy
minimization techniques for battery-powered systems with time-constraint. ACM transaction
on design automation of electronic systems, vol 12
Carter JL, Iyengar VS, Rosen BK (Sep 1987) Efficient test coverage determination for delay faults.
Proceedings of international test conference, pp 418-427
Chen G, Reddy SM, Pomeranz I (Oct 2003) Procedures for identifying untestable and redundant
transition faults in synchronous sequential circuits. Proceedings of international conference on
computer design: VLSI in computers and processors, pp 36-41
Cheng K-T, Chen H-C (Sep 1993) Delay testing for non-robust untestable circuits. Proceedings of
international test conference, pp 954-961
Cheng K-T (Dec 1993) Transition fault testing for sequential circuits. IEEE Trans Comput-Aided
Des Integrat Circuits Sys 12:1971-1983
Cheng K-T, Chen H-C (Aug 1996) Classification and identification of nonrobust untestable path
delay faults. IEEE Trans Comput-Aided Des Integrat Circuits Sys 15:845-853
Dasgupta S, Walthers RG, Williams TW, Eichelberger EB (Jun 1981) An enhancement to LSSD
and some applications of LSSD in reliability, availability and serviceability. Proceedings of
international symposium on fault-tolrant computing, pp 880-885
Devtaprasanna N, Gunda A, Krsihnamurthy P, Reddy SM, Pomeranz I (Oct 2005) A novel method
of improving transition delay fault coverage using multiple scan enable signals. Proceedings of
international conference on computer design: VLSI in computers and processors, pp 471-474
Dumas D, Girard P, Landrault C, Pravossoudovitch S (Oct 1993) An implicit delay fault simula-
tion method with approximate detection threshold calculation. Proceedings of international test
conference, pp 705-713
Eichelberger EB, Williams TW (1978) A logic design structure for LSI testability. J Des Automa-
tion Fault-Tolerant Comput 2:165-178
