Hardware Reference
In-Depth Information
a
a
STR STF
a
c
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STR STF
SC
1
h
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STR STF
e
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STR STF
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STR STF
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STR STF
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STR STF
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2
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STR STF
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STR STF
A full scan circuit
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c
SC
1
h
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Unt. Flts.
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SC
2
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STR
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STR
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g
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d
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STR
SC
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SC
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g
STR
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SC
2
LOC test with unsegmented scan chain design
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SC
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SC
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SC
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Unt. Flts.
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e
b
STR
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g
b
STF
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d
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d
SC
1
SC
1
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STR
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b
SC
2
Test generation with only segment 1 launching
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SC
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SC
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SC
2
Unt. Flt.
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STR
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d
i
SC
1
SC
1
b
b
SC
2
Test generation with only segment 2 launching
Fig. 3.28
An example illustrating higher TDF coverage in segmented scan designs
3.4
Summary
In this chapter basic fault models for defects that increase signal propagation de-
lays in digital logic circuits were presented together with methods to generate and
apply tests to detect modeled faults. Methods to detect small delay faults and de-
sign for test methods to improve delay fault coverage and reduce design effort were
discussed. There is a vast amount of literature on delay faults that could not be
reviewed in the chapter. Among the topics not discussed in the chapter are built-
in-self-test methods and fault diagnosis. Additional material and in-depth treatment
