Digital Signal Processing Reference
In-Depth Information
order to reduce the small-signal transconductance gain. This is done in order to
obtain a low sensitivity of the bias current to variations of the gate-source volt-
age of the current source. For exactly the same reasons, the pmos transistors
at the top of the schematic were biased 200 mV above their threshold voltage.
The next step in the determination of the node voltages of the circuit is to
divide the 1
.
2 V supply voltage among the transistors. The biggest chunk of
the voltage headroom, 600 mV, is consumed by the diode-connected transistors
(mn
3
). The remaining voltage is divided between the current sources at the top
of the schematic (300 mV over mp
1a
−
1d
) and the tail current source (300 mV
over mn
5
). The common-mode level of both the input and the output of the core
amplifier is 900 mV. Doing so provides enough space for a differential output
swing up to 400 mV
diff, ptp
, while none of the transistors will be pulled out of
the saturation region. The only node of which the voltage remains a variable
parameter is the drain voltage of mn
4
, the common tail current node of the
input transistor pair. This voltage automatically follows from the dimensions
of the gain transistor pair. Since the ratio between the widths of the gain and
loading transistors is already set by the target gain of the amplifier, the voltage
at node n1 of the loading pair is not an independent parameter.
The length of the transistors was determined by their actual function in the
circuit. All current sources were given a channel length of 0
.
65
m. The extra
parasitic drain capacitance is fairly low compared to the gate capacitor, thus
by increasing their length, the output resistance is improved without too much
penalty on the bandwidth of the amplifier. For the same reason, the lengths of
the gain and loading pair were chosen much smaller, 0
.
24
μ
m, because their
gates are connected to the input- and output-terminals and therefore a larger
gate capacitor would be immediately visible in the frequency performance plot.
There is still one more final parameter has to be set before the circuit can be
handed over to an automatic solver: the current through the transistors. Each
of the four top pmos current sources draws 200
μ
A from the power supply.
The current in each branch of the differential amplifier is equally split over the
gain and the loading transistor pairs. The total current of each differential pair
is then combined again in the tail current source: both mn
4
and mn
5
drain in
total 800
μ
A to the ground line of the power supply. Note that this total current
was determined based on a target output impedance (1
/g
mo
) of around 900
of transistors mn
3a,b
.
After running the automatic optimizer, the target widths of the transistors be-
come available and the process of fine tuning can be started. First of all, the
voltage level on node n1 of the loading pair must be verified, since this was
the only node of which the voltage was not explicitly set. As can be seen in
the schematic (Figure 7.6), the voltage level on this node is 405 mV, which
μ
