Digital Signal Processing Reference
In-Depth Information
Section 7.1, a tiny dc-offset will grow to a large problem further on in the
chain. By the introduction of a separate offset-compensation circuit on each
of the output nodes, deviations from the reference voltage are suppressed as
long they stay within the range of the offset compensation circuit. The output
of the offset compensation circuit is connected to the biasing transistors mp
1a
and mp
1b
.
Also note that only half of the bias current is controlled by the offset compensa-
tion circuit, while two other pmos current sources (mp
1c
and mp
1d
)aredriven
by the averaged output level of both compensation circuits. The reason for
this is nontrivial, but also quite easy to explain. Remark the two cross-coupled
capacitors between the output terminals and transistors mp
1c
and mp
1d
.In
combination with the resistors at the gates of those transistors, they form a
high-frequency zero which acts as a virtual inductance connected to the output
nodes of the core amplifier. This inductance can be tuned in order to obtain
some form of inductive peaking near the 3 dB cut-off frequency of the ampli-
fier.
4
Thanks to this low-quality tank, the 3 dB pole is then shifted to a slightly
higher frequency. The selection of the value of the cross-coupling capacitances
is quite crucial. If the cross-coupling factor is too low, the peaking will come
too late so that the bandwidth of the amplifier is not extended at all. If the
value of the cross-coupling capacitors is too large, peaking will not only occur
before the cut-off frequency, but also the quality factor of the virtual lc-tank
will be too high. In the best-case scenario, an unexpected peak will shows up
in the bode diagram. In worst case, a new astable multivibrator sees daylight.
5
The cross-coupling method becomes more reliable if some tuning flexibility is
added. The first available tunable capacitor is found in the form of the deple-
tion layer capacitor of the reverse biased pn-diode formed by the drain and the
n-well of transistors mp
1c
and mp
1d
. Instead of connecting the n-well implants
of these transistors to the power supply rail, they were connected to a separate
biasing node. When the reverse voltage over this diode is increased, the width
of the depletion layer will increase and the capacitance at the output terminals
of the amplifier is reduced. Within certain limits, the bandwidth of the ampli-
fier can be tuned so that the stability of the amplifier can be guaranteed over a
broad range of process variations.
Also shown in the schematic of Figure 7.6 are the actual transistor values that
were used during the design.
6
The design journey that leads to the final layout
was started by determining the bias voltages of all nodes in the circuit. First
of all, the overdrive voltages of the tail current sources (mn
4
and mn
5
)were
assigned. The overdrive voltage should be chosen relatively high (200 mV) in
4
This was done using repeated parasitic extractions on the layout.
5
Provided that the chip is not packaged.
6
Parameters of the 0
.
13
μ
m technology: V
supply
=
1
.
2V,V
tn
≈
260 mV, V
tp
≈
280 mV, l
min
=
0
.
12
μ
m.
