Digital Signal Processing Reference
In-Depth Information
bandwidth of about 1 GHz in combination with a voltage gain of 30 dB. Finally,
the optimum scaling factor between the stages is finally given by (7.20):
x
=
1
/
n
g
mo
R
load
1
/
8
√
1
.
1mS
=
·
50
=
1
.
43
(7.20)
Design of the core amplifier cell
The core schematic of the nonlinear loaded amplifier, this time extended
with the supporting bias circuitry is shown in Figure 7.6. Instead of a single
common-mode feedback circuit controlling the average voltage level at the
output, both terminals have their own voltage-regulation circuit. The reason
behind this choice is that dc-coupling is going to be used as the intercon-
nect method for the subsequent core amplifiers. As was already explained in
1.200V
nVdd
I
= 200
A
V
GST
= -200mV
μ
900mV
R=5k
r
o
=14kOhm
R=2.5k
V
ref
V
ref
V
cmfb-
V
cmfb+
MP
1A
MP
1C
MP
1D
MP
1B
40fF
V
o
ut-
V
out+
900mV
900mV
I
= 200
A
g
m
=2.2mS
r
o
=14kOhm
μ
V
in+
V
in-
MN
3A
MN
2B
MN
3B
V
GST
= 132mV
MN
2A
I
= 200
A
g
m
=1.1mS
r
o
=21kOhm
μ
900mV
405mV
I
bias1
= 400
A
V
GST
= 200mV
μ
V
bias1
MN
4
V
GST
= 273mV
300mV
I
bias2
= 400
A
V
GST
= 200mV
μ
V
bias2
MN
5
Figure 7.6.
Detailed schematic of the open-loop core cell, with supporting circuitry.
At the top is the differential offset compensation circuit, combined with
capacitive cross-coupling to obtain some peaking around the 3dB cut-
off frequency of the amplifier chain. It should be stressed that the latter
measure cannot improve distortion suppression (see text).
