Digital Signal Processing Reference
In-Depth Information
3dB bandwidth [GHz]
0dB gain
Higher gain requires larger
optimal number of stages.
(indicated with a dot )
2.0
1.5
5dB/step
Number of stages too large:
Bandwidth reduced due to
large number of poles.
1.0
40dB gain
Number of stages too small:
0.5
System collapses under
heavy load of upscale factor.
settings: g
mi
=2mS, R
load
=50Ω, f
T
=30GHz
Number of stages
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 7.5.
Theoretical bandwidth of the open-loop amplifier versus the number of
stages (Formula 7.19), simulated for different gain settings (sweep from
0 to 40 dB). It was supposed that the
f
T
is 30 GHz, taking the load of
the transistors into account.
to less than 35 GHz. Finally, the total bandwidth of the complete
n
-stage chain
can be expressed by a combination of Formulas (7.15), (7.16) and (7.18):
2
n
ω
3dB, n-stage
=
ω
3dB, single stage
·
−
1
2
n
f
t
, input
A
v, total
k
+
·
=
−
1
(7.19)
1
n
√
g
mo
R
load
+
1
n
Figure 7.5 shows the bandwidth of the amplifier chain versus a sweep over the
number of stages. The total required voltage gain (
A
v, total
) was also varied from
0 to 40 dB. In this figure it is clearly visible that two opposing effects are at
work at the same time. If the number of stages is too low, capacitive load due to
upscaling the amplifiers will dominate. On the other hand, the total bandwidth
of the chain will drop for a higher number of stages. This despite the reduced
load on each separate core amplifier. In order to get a grasp on the sensitivity
of the results, it is also interesting to play around with the parameters. The
main observation should be that - at least for reasonable values - the number
of stages always stays within the range of
n
3 to 10. From this graph it can
also be observed that the eight-stage amplifier is a good candidate to achieve a
=
