Digital Signal Processing Reference
In-Depth Information
Bandwidth versus latency
There is one noteworthy difference between the analog multistage
buffer and its digital counterpart though. In the former case, high band-
width is obviously one of the major design goals. In the latter case,
rather low latency instead of a high bandwidth is preferred. For mini-
mum latency, it can be shown [Com96] that each subsequent stage of
the digital buffer must be upscaled with a factor
e
(Euler's number).
While
e
is the optimum scaling factor for a minimum-delay digital buffer, con-
cluding that the same magic
e
-number also holds for the tapered open-loop
amplifier is a bridge too far for the self-respecting analog designer. First of
all, the open-loop nature of a baseband amplifier does not require that phase-
delay becomes the most important design criterion: the variables in the design
space of an analog amplifier include power consumption, chip area, linearity,
voltage swing, noise figure, maximum output load, gain and bandwidth.
3
The
following paragraphs describe the design strategy that was followed during
the implementation of the eight-stage amplifier. Also, the correlation between
several system parameters will be explained.
The upscaling factor of the tapered amplifier
First of all, the primary goal during the design of this amplifier was maximum
bandwidth. This in contrast to a commercial design, where the target would
rather be maximum power efficiency. Or minimum design effort. The band-
width is then chosen in order to meet the minimal requirements of the target
application. Starting from the first stage of the amplifier, each of the subse-
quent stages is upscaled with a factor
x
and directly drives a small resistive
or large capacitive load. In the design presented here (Figure 7.3), the final
stage drives the 50
impedance of a vector network analyzer. If impedance
matching between the last stage and the measurement equipment is required,
the transconductance of the loading pair in last stage must be 20 mS. As a
comparison, the output impedance (1
/g
mo
) of the first, smallest amplifier in
the design is 900
. Starting from the output impedance of the first stage, the
target impedance in the last stage (
R
load
=
50
) and the number of stages (
n
),
the correct scaling factor is given by (7.15):
1
x
=
√
g
mo
R
load
(7.15)
n
3
Gain-bandwidth (gbw) is not very meaningful in the figure-of-merit of a multistage amplifier.
