Digital Signal Processing Reference
In-Depth Information
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Figure 7.3.
Schematic of two cascaded core cells in the amplifier chain. Each section of the
amplifier is upscaled with a factor
x
Equation (7.20) in order to drive a 50
load
with a maximum bandwidth. Note that each of the core amplifier cells has its
own dedicated offset compensation circuit. A more area-efficient solution would
perform the offset compensation over several core cells at once, at the cost of
some distortion performance.
Before the upscaling factor
x
can be determined, one more missing parameters
must be determined: the optimal number of gain stages (
n
) in the chain. At this
moment, things will get a little bit more complicated since several interrelated
design parameters play a role in our search for the optimum number of stages.
The following reasoning clearly shows the counteracting forces that play in
this optimization problem. First of all, the 3 dB bandwidth of the complete
chain is defined both by the bandwidth of one single stage and the number
of stages. A reduction in the number of stages will require a larger upscaling
factor between two stages. Which in his turn results in an increased load at
the output of each stage. The bandwidth of a single stage decreases and so
does the bandwidth of the complete amplifier. However, one parameter has
not been taken into account yet: the total voltage gain (
A
v
) of the amplifier. If
A
v
is chosen as fixed, independent design parameter, the voltage gain of each
single stage depends on the number of stages in the chain. The reader should
remember from Section 7.2, that the gain of the open-loop stage was controlled
by the 1
/g
mo
output impedance of the diode-connected load transistors. As a
consequence, changing the gain of the open-loop stage inevitably also changes
its bandwidth. Which also reflects on the overall bandwidth of the chain. A
rough sketch of all interrelated parameters in the optimization problem can be
found in Figure 7.4.
