Digital Signal Processing Reference
In-Depth Information
be easily adjusted to a wide range of varying input signal conditions. There are
also less obvious advantages of cascading multiple amplifiers: whenever the re-
ceived signal becomes stronger and less stages are necessary to bring the signal
to the required output level, the overall bandwidth of the remaining stages will
improve, generating some opportunities to scale the power consumption even
more than would be expected at first sight.
Architecture of the open-loop amplifier
The core cell of the open-loop amplifier, without the supporting circuitry to
maintain the correct operating point, is shown in Figure 7.2. It is built around a
simple differential pair with an active load that consists of a second differential
pair in diode configuration. The voltage gain of this configuration is set by
the transconductance ratio
g
mi
/g
mo
between the gain- and the load pair. For
maximum gain, the load pair should be omitted. In this case, the output current-
to-voltage conversion is taken into account by the parasitic output impedance
of the current sources and the gain pair itself.
Of course, the higher the impedance at the output, the lower the bandwidth.
When a higher bandwidth is required, the gain of the loading pair can be in-
creased up to the point where the dimensions of both the in- and output pair
become equal. The 1
/g
m
impedance of the active load will dominate the output
impedance and the voltage gain of the amplifier is (approximately) reduced to
nVdd
Local feedback circuit
mode voltage in range.
V
cmfb-
V
cmf
b+
keeps output common-
V
o
ut-
V
o
ut
+
C
parasitics
V
in+
V
in-
g
mo
g
mi
g
mi
g
mo
i
diff
Cut-off frequency is def-
and 1/g
mo
of the active load.
ined by output capacitance
I
gain
i
diff
Voltage gain of amplifier
is determined by g
mi
/g
mo
.
I
load
(parasitics are ignored)
Figure 7.2.
Core cell of the open-loop amplifier. The differential output current
of the gain stage is directly injected into a second, diode-connected
differential pair. Common-mode signal suppression is determined
by the parasitic output impedance of the bias current cells feeding
both transistor pairs.
