Digital Signal Processing Reference
In-Depth Information
unity gain. At this point, the maximum bandwidth of the amplifier is achieved.
It is defined by the 1
/g
m
load resistance in parallel with the capacitance of all
devices connected to the output terminal: these include the drain capacitances
of gain and load transistors, the output capacitance of the current source, the in-
put capacitance of the subsequent stage, the common mode feedback circuitry
and last, but not least, some wiring capacitance. In other words, the gain pair
will experience a load that is at least
N
5
...
6 times larger than its self-
loading capacitance, at least for unity gain. Provided that the voltage gain of
the amplifier will be in the range of 0
...
6 dB, a reasonable estimation for the
3 dB bandwidth of a single stage is approximately
f
T
/
12
=
=
8 GHz (6 dB gain,
f
T
=
100 GHz) up to a theoretical maximum of
f
T
/
5
=
20 GHz (unity gain,
=
f
T
100 GHz). In practical implementations, the effective bandwidth that is
achieved will even be lower than this value.
In order to achieve a better voltage gain, multiple stages of a single core cell
are embedded in a chain (The mathematical derivation for the equivalent 3 dB
bandwidth of a cascaded amplifier is included in Section A.1). For example,
suppose an eight-stage amplifier in which the bandwidth of each core cell is
bw
3dB, core
8 GHz. From Formula (A.14), it follows that the overall 3 dB
bandwidth of the eight-stage amplifier is three times less than the bandwidth
of its composing stages. In worst case, for an
f
T
=
100 GHz technology, an
experienced designer should end up with a bw
3dB
around 2
.
5 GHz, which is
still remarkably better than what can be achieved in a closed-loop approach.
=
7.3
Improving linearity using a nonlinear load
It was mentioned earlier in this chapter that the nonlinear transconductance
characteristic of the gain transistors in a differential pair can be suppressed
by employing various strategies. For example, even-order distortion is effec-
tively eliminated by using a differential topology, while the signal-of-interest
is situated in the differential domain. Odd-order distortion on the other hand,
is suppressed by inserting the amplifier in a feedback structure, but this ap-
proach fails at higher frequencies. While the distortion suppression of feed-
back systems is mainly based on the trade-off between gain and linearity, the
suppression mechanism of the open-loop amplifier discussed in this chapter is
completely based on the linearization of the transconductance gain by the in-
verse i-to-v characteristic of a nonlinear active load. At the lower end of the
frequency spectrum, the performance of the feedback topology is unrivaled if
compared to the open-loop linearization technique. But in terms of suppression
bandwidth it is undoubtedly the latter one that beats the lot.
Furthermore, it has already been discussed that the voltage gain of the non-
linear loaded amplifier from Figure 7.2 can be controlled by adjusting the
transconductance ratio
g
mi
/g
mo
between the gain and the loading transistors.
