Digital Signal Processing Reference
In-Depth Information
1a / b: Downconversion
mixer and receive
window circuitry.
2a / b: Variable gain
amplifier and clock
distribution network.
3a / b: Current mode
analog output buffers.
I/Q signal chain
baseband outputs.
1a
2a
3a
Differential RF
antenna inputs.
RF-GND
1b
2b
3b
External clock
reference signal.
General purpose
buffer outputs.
4
5
6
DO NOT EAT
4: High-speed prescaler
and postscaler section
5: Multiphase clock
generator circuits.
6: General purpose
output buffers.
Figure 6.10.
Chip microphotograph of the pulse-based prototype receiver. Each
of the nine subblocks is surrounded by a power supply and decou-
pling ring, underneath which a ring of substrate contacts prevents
that clocking noise leaks into the analog subsection.
of the chip contains at the left subblock (4) a high-speed prescaler (operation
of which was verified up to 16 GHz) and the divider chain. The middle block
(5) contains the multiphase clock generator, which is used as accurate time ref-
erence for the receive window circuitry. The outputs of the delay cells of the
clock generator are buffered by regenerative driver latches. The latter ones are
necessary to drive the capacitive load of the clock distribution lines, which are
clearly visible as the 4
2 vertical lines protruding upwards from the multi-
phase subblock (5) into the analog signal chain (2a/b).
Remark that the clock lines are routed perpendicular to the i/q signal chain
in order to minimize in-coupling clock noise. For the same reason, the clock
lines organized in pairs of differential signal conductors. Also, the distribu-
tion lines have equal lengths to equalize their load on the clock drivers. The
microphotograph also shows the power distribution grid which surrounds each
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