Digital Signal Processing Reference
In-Depth Information
chain. Because the open-loop baseband amplifier in the prototype receiver uses
dc-coupled sections, a growing offset voltage builds up after a few stages. In
the prototype chip, this issue was solved by sampling the differential offset
voltage on a large interstage coupling capacitor after every two sections of the
baseband amplifier. However, the bandwidth requirements of the amplifier are
doubled in this rz approach.
14
In the implementation of the improved baseband amplifier of Section 7, this
problem was circumvented by the introduction of two independent common-
mode feedback (cmfb) circuits on each differential output node. In this ap-
proach, the return-to-zero format is avoided, but signal frequencies within the
control range of the cmfb circuit will be suppressed. Fortunately, issr can
be used to reconstruct the missing portion of the signal. For example, when the
offset compensation circuit cuts in below 1 MHz, while the bandwidth of the
baseband signal is 50 MHz, the implementation losses are less than 0
.
09 dB.
Also remark that in Figure 6.9, the qpsk constellation is not symmetrically
centered around the origin of the i/q plot. This is because the window circuit
is erroneously located behind the downconversion mixer, which causes charge
injection within the frequency band of the baseband amplifier.
Not visible in Figure 6.9, but clearly present in the spectrum plot of the base-
band signal is a large spectral component at the clocking frequency of the offset
compensation circuit. Part of the dc offset voltage in the baseband signal chain
is in fact caused by self-mixing of the offset compensation clock signal. The
consequence is that it cannot be removed by simply ac-coupling the stages of
the amplifier. The important lesson learned here is to stay out of the frequency
band of the signal-of-interest, especially when dealing with very weak signal
components as those encountered in the signal chain in the front-end of a re-
ceiver (see Section 6.1).
6.6
Summary of the pulse-based receive unit
To conclude this section, Figure 6.10 shows the chip microphotograph with an
overlay indicating the different building blocks of the receiver. The core area of
the receiver measures 930
m. Clearly visible on the floorplan of the chip
is the quadrature signal chain of the prototype receiver. The differential rf sig-
nal inputs are located at the left side, while the baseband outputs (i/q) can be
found at the right side of the chip. From the left to the right, one can distinguish
the downconversion mixers with integrated windowing circuitry, a dual base-
band variable gain amplifier and the output driver section. The bottom section
×
930
μ
14
The minimum sample rate of the adc is not affected if the converter is synchronized to the sample
speed of the receiver using the multiphase clock trigger signal. However, for an asynchronous conversion
technique, the bandwidth of the adc would be more than doubled.
