Digital Signal Processing Reference
In-Depth Information
Voltage level of
Variable gain amplifier
User is automatically
cascode transistors
in mixer front-end.
settings. Independent
control over I/Q lines.
informed if errors occur
during transfer.
Controls symbol rate.
Delay between Gate1/2
General purpose output
Bypass with external
time reference possible.
controls duration of the
receive window.
buffers can be connected
to several internal signals.
Figure 6.8.
The gui interface of the prototype allows the user to quickly load set-
tings into the chip, compare the performance of different chip samples
and store settings for future reference.
by four output buffers, two of which are dedicated to the analog signal chain
while the remaining two serve as general purpose drivers for measuring inter-
nal voltage levels and (baseband) analog and digital signals. To reduce tran-
sients on the supply lines, a current-mode differential topology was chosen for
the output buffers, even for digital signaling. Finally, off-chip rf baluns (0
.
4-
450 MHz, 2:1 ratio) are used for the differential to single-ended conversion, to
provide galvanic isolation and to transform the 50
impedance of the load to
the output impedance of the on-chip drivers.
Bad science at it's best
During the first debugging tests of the prototype receiver, a minor but
practical problem was experienced with the on-chip memory bus. It
seemed as if the contents of the static memory got corrupted about
once or twice in an hour. More regular updates of the memory contents
could resolve this problem most of the time, but intermittent failures
continued to occur. After some digging, it turned out that the culprit
was the high input impedance of the clock line between the external
