Digital Signal Processing Reference
In-Depth Information
controller and the on-chip memory. A few centimeters of interconnect
wiring is able to build up a sufficient amount of voltage noise to trigger
the clock line of the memory once in a while. As a result of this, the
data vector is shifted by one or more positions, thereby invalidating all
internal settings.
A possible solution to this are differential encoded data- and clock
lines. In the measurement setup of the prototype, the mysterious mem-
ory corruption issue (mmci) was solved by placing a termination resis-
tor close to the clock input lead of the receiver. An external interferer
cannot provide the power needed to reach the threshold voltage of the
clock line. A time consuming mistake!
6.5
Experimental results for the prototype chip
The measurements of the prototype receiver were performed with an external
reference clock running at 2
.
25 GHz. The on-chip high-speed prescaler of the
receiver is injection-locked on the third-order harmonic of this signal, which
results in an internal reference clock of 6
.
75 GHz. The off-chip oscillator signal
is presented to the prescaler in a differential format. This allows the user to fine
tune the accuracy of the quadrature outputs of the prescaler. At the output of
the prescaler, the four 90
◦
shifted signals are applied to the lo-inputs for the
i/q downconversion mixer network. This makes that the center frequency of
the pulse-based receiver is exactly 3
.
375 GHz.
Since the prototype chip includes a receiver, but lacks the hardware at trans-
mission side for a fully operational wireless link, the signal applied to the rf
inputs was generated by a multi-port data generator.
13
Two of the medium-
speed ports of this generator were used to generate the differential clock signal
(2
.
25 GHz), while a third high-speed port was used to generate a 13
.
5 Gbps
serial bit stream. The accuracy of the latter one is sufficient to generate a test
signal with a main lobe frequency at 3
.
375 GHz and four different possible
phases with respect to the lo reference signal. The internal data registers of
the generator were programmed to rotate the phase of the test signal between
two consecutive receive slots, which results in a qpsk modulated carrier sig-
nal. A pulse-like qpsk transmission was achieved by limiting the duration of
a pulse burst to 20 periods (40 data bits, period T
pulse
=
3ns).
Remark that the signal of the data generator is not entirely compliant with
the requirements prescribed by the fcc (see Section 6.5), which is for several
reasons. First of all, part of the sidelobe power oversteps the spectral mask im-
posed by the fcc due to the steep edges of the rectangular transmit window.
13
Agilent Parbert 81250 with 13.5 Gbps modules.
