Digital Signal Processing Reference
In-Depth Information
optical isolation
data
RS-232
clock
RTOS
memory control
voltage level
converter
verify written data
4-bit memory
D_in
4-bit memory
D_in
4-bit memory
D_in
d
0
d
1
d
2
d
3
d
0
d
1
d
2
d
3
d
0
d
1
d
2
d
3
d
0
d
1
d
2
d
3
Vref
FF
FF
FF
FF
4-bit DAC
3-to-8 line decoder
D
Q
D
Q
D
Q
D
Q
out
8 chan. multiplexer
Master stage
Slave stage
baseband in
D
Q
2
2
2
VGA
CLK
Q
TSP D-flipflop
Example 1:
Example 2:
Memory bus controls
on-chip reference voltage.
Memory bus controls
analog multiplexer of VGA.
TSP: watch out for race-conditions!
Figure 6.7.
The prototype receiver is controlled by an on-chip memory bus which
allows to control and measure over 50 in- and output nodes. The
memory bus itself is controlled by an external microcontroller. The con-
troller, in his turn, is connected to a computer which presents a conve-
nient interface to the user.
binary coded da-converters. The output signal of the binary dac's is then used
to alter the load impedance of the analog delay cells (see Section 6.2). It is clear
that the user interface prevents that the user is distracted with the technical de-
tails of the measurement setup, while it becomes very convenient to load a set
of predefined test configurations on a number of prototype setups. Also, set-
tings can be linked to interesting measurement results and stored for further
analysis later on.
Thanks to this programmable measurement shell which was built around the
prototype receiver, the number of access points was reduced from 88 to only
22 bonding pads, without having to compromise on the accessibility of internal
circuit nodes. The only external components required to do this are the three-
wire memory bus, an external reference voltage from which the common mode
voltage of the signal chain is generated and a single bias current for the em-
bedded ad-converter circuits. The connection to the outside world is managed
