Digital Signal Processing Reference
In-Depth Information
At the next higher level in hierarchy, the output of one memory subblock
connects to the data input of the subsequent block, which results in a chip-wide
serial register. The input of the first register is made available as an external pin,
as is the clock line of the memory bus. The system bus is controlled by an ex-
ternal microcontroller, which applies the correct pattern of logic signal levels
to the data and clock lines in order to shift a vector of settings into the receiver.
The output of the memory bus is also made available on an external 'data out'
pin,
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which allows the controller to read back information at the output of the
memory bus. A control word is always read twice into the memory bus. In this
way, the memory controller checks for transmission faults and flags an error
to inform the user about this problem. For all this, the controller only needs
to know the length of the settings vector and the sequence of activation of the
control signals to clock a data bit into the memory bus. However, it does not
know about the structure of the memory map of the receiver.
For this purpose, the controller communicates with a computer over an opti-
cally isolated RS-232 interface (Figure 6.7). On the host computer, the user
is presented a user interface displaying the chip floorplan of the receiver
(Figure 6.8). On this floorplan, the structural blocks (mixer, vga, multiphase
generator) of the prototype receiver are visualized. Along with each block, the
user is also presented with a number of interactive controls related to that spe-
cific block. For example, the mixer block contain a gui slider which allows to
control the bias voltage of the cascode transistors. Both the i- and the q-mixer
are fed by the same antenna signal. Adjusting the mutual input impedance
between the mixers by varying the gate voltages of their respective cascode
transistors alters the ratio of how incoming signal power is distributed among
the two stages. This is an interesting possibility in light of the pulse-based
wideband receiver discussed before, where the power from a single physical
antenna has to be split among multiple receive units.
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Another example is the
variable gain amplifier. The user can select the number of vga-stages that are
activated, while the total gain of the current setting is displayed for operational
convenience. In the background, the gain control is translated to the correct set-
tings of the internal multiplexers of the receiver. The settings are subsequently
packed in a new control vector, handed over to the microcontroller which trans-
fers it to the memory bus of the prototype chip.
A similar strategy is used to adjust the delay lines of the multiphase clock gen-
erator. For the configuration of this block, the memory bus drives four on-chip
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The data output pin of the memory bus has an internal weak pull-up resistor. This pin is multiplexed with
an emergency master clock input for the multiphase clock generator.
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Remark that this is in sharp contrast with narrowband architectures. To a certain level, power is less of a
problem here since the surplus input impedance (gate capacitance) formed by multiple parallel stages can
be taken into account in the matching network of the antenna. Tuning out load capacitances is not an option
for wideband networks, though.
