Digital Signal Processing Reference
In-Depth Information
is 1 GHz, the noise floor at the antenna terminal is given by kTB =
83
.
8dBm.
If the duty cycle of the receive window is 10%, the total channel noise power
that is allowed to enter in the front-end of the receiver is
−
−
93
.
8dBm. At the
85
.
6dBm.
9
From
this, it can be calculated that the noise figure of the receiver is nf
=
output of the mixer, the kT/C noise power is approximately
−
8
.
2dB.
This is a rather high value which is caused by the absence of an lna in the
prototype receiver. This noise figure can be improved by putting a low noise
amplifier in front of the receiver. For example, an lna with a noise figure of
2 dB and a gain of 3 dB would reduce the overall noise figure of the receiver to
4
.
4dB.
10
However, adding an lna to the front-end should be done with great
caution, because the lna is located in front of the receive window and is ex-
posed to the full interferer power. In a hostile channel with high interference
levels, an lna may cause more harm than good [Ver06]. The prototype receiver
itself, without active gain element at the input, exhibits an input-referred third-
order interception point (iip
3
)betterthan
−
1dBm.
6.4
Design for testability
During the design of the receiver, considerable time and effort was put in the
testability of the system. The prototype receiver has a reasonable number of
internal nodes and voltage settings for which it would be interesting to have
external control lines or an access point for measuring purposes. For this reason
and to prevent excessive complexity in the measurement setup, the receiver has
been equipped with an on-chip memory bus and an array of analog and digital
supporting circuits. With this approach, over 50 in- and output nodes could be
successfully merged in a resource-efficient measurement shell around the core
of the receiver.
The framework of the control system is based on an on-chip static memory,
consisting of a number of stacked memory cells. Each of these single-bit cells
is implemented by a true single-phase (tsp) D-flipflop. Such a tsp-based cell
has - apart from power supply - only three connections: one input data bit,
an output bit and a single clock line, which is shared among all memory cells.
Data bits are shifted in a serial way from one memory cell into the next, so the
interconnect pattern between the cells is limited to only two wires. Instead of
being centrally located, the memory bus is divided over a number of small 4-bit
subblocks, spatially distributed over the floorplan of the chip. This way, the
data outputs of the memory bus could be located precisely where needed, pre-
venting that wide bundles of wires 'fan out' from the memory unit to specific
locations elsewhere in the recei
ver.
9
The real part of the mixer output impedance is 2 k
. Using Equation (6.1), calculating the rms noise
power is straightforward.
10
Noise factor of a cascaded system: f
tot
=
f
1
+
f
2
−
1
f
3
−
1
g
1
g
2
+
+···
g
1
