FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 265

power dissipation [1, 4, 5]. The two major categories of defects occur because of
interconnections and power dissipation.
The unreliability of nanoscale devices is a consequence of the inherent
variability in fabrication processes and the physical principles that govern their
operation. Self-assembly methods may have to be used at dimensions below those
for which conventional lithographic-defined subtractive processing methods are
used. Since variability and imprecision are inherent in such self-assembly pro-
cesses, it is estimated that a significant number of devices, up to many percent,
may suffer from manufacturing defects. The other source of unreliability is due to
the physical principles of these devices that cause reduced noise tolerance and
higher susceptibility to external influences, such as electromagnetic interference,
thermal perturbations, and terrestrial radiation, resulting in in-service transient
faults.
The problem of interconnects is due to a number of fundamental challenges.
These are (i) the geometrical challenge of interconnecting devices at the nanoscale
dimensions at high speed and bandwidth; (ii) the process of interfacing these
devices with the macroscopic world; and (iii) the challenge of transforming long-
distance communications to short-distance communications for nanodevices that
have low drive capabilities. To tackle some of these challenges, fabrication
processes for producing aligned wires and highly regular, homogeneous and
locally connected parallel architectures have been proposed.
The other challenge is thermal power dissipation that comes from device
switching energy and the energy needed for driving signals. Due to this, there is a
trade off between clock speed and device density—clock speeds need to be
decreased for high device densities, and densities need to be lowered for high
clock speeds. The problem of power dissipation sets a general limit to the
operational speed of any charge-based nanodevice. To solve these problems,
researchers are looking at approaches like charge recovery [6], reversible comput-
ing [7], and adiabatic computing [8].
10.2. FAULT TOLERANCE THROUGH REDUNDANCY
For the management of defective and error-prone devices, several fault- and
defect-tolerant nanoarchitectures have been proposed in order to aid the reliable
integration of nanodevices, hence allowing the demonstration of their full
potential [9]. Techniques such as redundancy and reconfiguration are used in
such architectures to achieve defect and fault tolerance. Here we discuss various
redundancy techniques commonly used to achieve fault tolerance.
10.2.1. Structural Redundancy
Redundancy has been widely used for fault tolerance in hardware. A structurally
redundant architecture is one which mitigates the effects of faults in the devices
and interconnects that make up the architecture and guarantees a given level of