FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 266

reliability. Various structural redundancy-based techniques such as triple modular
redundancy (TMR), Cascaded triple modular redundancy (CTMR), von Neu-
mann multiplexing and their variations have been proposed to provide fault
tolerance in hardware. As opposed to structural redundancy, temporal redun-
dancy entails repetition of the same computation if the computation fails to
compute correctly. A classical temporal redundancy mechanism used in hardware
is based on checkpoints and roll-back recovery [10, 11]. This chapter focuses on
fault tolerance techniques based on structural redundancy.

10.2.1.1. Triple Modular Redundancy (TMR). The concept of TMR [12] is
to have three functionally identical units working in parallel and comparing their
outputs with a majority (MAJ) gate to produce the final output. The units could
be gates, logic blocks, logic functions, or functional units. TMR provides a
functionality similar to one of the three parallel units but provides a better
probability of working [12]. The MAJ gate is a single failure point and three of
these can be used instead of just one to improve the reliability of the system
further.
The main drawback of simple, modular level TMR technique is that it does
not provide robust error recovery mechanisms [13]. For example, if the triplicated
units in TMR architectures have random logic with sequential elements and any
one of the units are in error, there is no mechanism by which such an error can be
detected until it manifests at the output of the modular unit. At that point in the
execution of the system, the internal states of the erroneous and nonerroneous
redundant modules will be inconsistent; Ref. 13 discusses the significance of
feeding back the voted result to all the voted sequential elements to resynchronize
all the redundant modules and avoid error build up. This implies that a Boolean
network needs to be apportioned into combinational and sequential parts; then,
redundancy may be inserted. This is shown in Figure 10.1 where triple MAJ gates
are used along with feedback.

10.2.1.2. Cascaded Triple Modular Redundancy (CTMR). CTMR [12] is
similar to TMR, wherein the units working in parallel are TMR units combined

Combinatorial
logic

Combinatorial
logic

Sequential
logic

Sequential
logic

Sequential
logic
MG = Majority gate

Figure 10.1. TMR for sequential and combinational logic.