FAULT- AND DEFECT-TOLERANT ARCHITECTURES FOR NANOCOMPUTING - Bio-Inspired and Nanoscale Integrated Computing - page 264

TABLE 10 . 1 . Parameters that have Improved Due to feature Scaling [1]
Parameter Example

Integration Level Components/chip, Moore's law

Cost Cost per function

Speed Microprocessor clock rate, GHz

Power Laptop or cell phone battery life

Compactness Small and light-weight products

Functionality Nonvolatile memory, imager

The scaling of CMOS technology has faced many barriers, but clever
engineering solutions and new device architectures have thus far broken through
such barriers. However, the size of a silicon atom will be an indisputable barrier in
CMOS scaling [2]. Since 2001, the ITRS Roadmap has challenged the practicality
of CMOS scaling projections beyond MOSFET channel lengths of 9 nm and has
addressed the need for non-CMOS technologies.
In the recent past, a number of novel non-CMOS nanotechnologies have
emerged that have shown potential in enhancing the CMOS platform; they have
also demonstrated promise developing fundamentally new approaches to infor-
mation processing. Chemical self-assembly of molecular devices is one such
nanotechnology that has been proposed for the development of reconfigurable
molecular nanofabrics. Some of these nanotechnologies have led to the develop-
ment of exciting memory and logic nanodevices. Engineered tunnel barrier
memory, polymer memory, and molecular memory are some of the novel
nanomemories under research, whereas CNTs, RTDs, molecular and spin devices
are some of the non-CMOS logic devices that have matured significantly. These
logic devices are predicted to have high switching speed, low power consumption,
and good demonstrations of scaling potential.
These nanodevices represent charge-based logic and their scaling is limited by
the minimum switching energy per binary operation, also called the thermody-
namic limit [3]. Beyond this limit, the challenge is to invent and develop
nanotechnologies based on something other than electronic charge. Ferromag-
netic logic and spin gain devices have been identified as some of the first potential
non-charge-based devices.

10.1.2. Challenges
Nanoelectronics has advanced appreciably in the recent past, and it has shown
potential for large scales of integration, specifically on the order of a trillion (10 12 )
devices in a square centimeter. But at the same time, some of the characteristics of
these nanodevices and their fabrication methods pose prominent limitations to
such ultra-scale integration. Some of these characteristics are manufacturing
defects, unreliable device performance,

interconnect limitations, and thermal