Internal Memory Configuration and External Expansion - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 736

used to implement address decoders for their ability to implement product terms of many
variables. The Generic Array Logic (GAL) devices are produced by Lattice Semiconductor.
The Simple Programmable Logic Devices (SPLDs) are produced by Atmel. Both ABEL and
CUPL are simple hardware description languages that are very suitable for describing circuit
behaviors for address decoders. ABEL is supported by Lattice Semiconductor, and CUPL is
supported by Atmel.

14.8.3 Timing Verification
When designing a memory system, the designer needs to make sure that timing require-
ments for both the microcontroller and the memory system are satisfied. In a read cycle, the
most critical timing requirements are the data setup time ( t DSR , parameter 10) and data hold
time ( t DHR , parameter 11) required by the HCS12 microcontroller. In addition, the designer must
make sure that the address setup time and hold time requirements for the memory devices are
met. The control signals needed by memory devices during a read cycle must be asserted at the
appropriate times.
In a write cycle, the most critical timing requirements are the write data setup time and
write data hold time required by the memory devices. As in a read cycle, the address setup time
and address hold time must also be satisfied. Control signals required during a write cycle must
also be generated at proper times.

14.9 Memory Devices

The control circuit designs for interfacing the SRAM, the EPROM, the EEPROM,
and the flash memory to the HCS12 MCU are quite similar. The following sections illus-
trate how to add SRAM and EEPROM chips with the 128K × 8 organization to the HCS12

microcontroller.

14.9.1 The K6R1008C1D
The K6R1008C1D is a 128K 8 bit asynchronous SRAM from Samsung that operates

with a 5-V power supply. The K6R1008C1D has a short access time (10 ns) and three-state
outputs. The pin assignment of the K6R1008C1D is shown in Figure 14.35. The address sig-
nals A16, . . . , A0 select one of the 128K locations within the chip to be read or written. Pins
I/O8, . . . , I/O1 carry the data to be transferred between the chip and the microcontroller. The
chip-select (CS) input allows/disallows the read/write access request to the K6R1008C1D.
The OE signal is the output-enable signal. When the OE signal is high, all eight I/O pins will
be in the high-impedance state.
Depending on the assertion times of control signals, there are two timing diagrams for the
read cycle and three timing diagrams for the write cycle (shown in Figures 14.36 and 14.37). The
values of the related timing parameters for the read and write cycles are listed in Table 14.10.
In Figure 14.36a and b, the CS signal must be asserted for at least t RC ns during a read cycle.
The signal that is asserted the latest determines the time that data will become available. For
example, in Figure 14.36b, the OE signal is asserted the latest; therefore, data becomes valid t OE
ns later. Data pins will go to the high-impedance state t OHZ ns after the OE signal goes to high
or t HZ ns after the CS signal goes to high.
In Figure 14.37a, the OE is controlled by a signal. Whenever the MCU wants to write data
into the SRAM, the OE signal is pulled to high. In Figure 14.37b and c, the OE signal is tied to

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