Hardware Reference
In-Depth Information
Example 14.15
▼
Suppose that a designer is to design an HCS12DG256-based embedded product that requires
256 kB of external 16-bit SRAM, 256 kB of 16-bit EEPROM, and a parallel peripheral interface
(PPI) that requires only 4 bytes of address space. The only SRAM available to this designer is
the 128K 3 8 SRAM chips (this chip has 128K locations with each location containing 8 bits).
The only available EEPROM is the 128K 3 8 EEPROM chips. Suggest a workable memory space
assignment.
Solution:
The designer is to design a 16-bit-wide memory system using the 8-bit-wide SRAM
and EEPROM chips. Two 8-bit-wide memory chips are needed to construct a 16-bit memory
module. One 16-bit-wide SRAM module can provide the 256-kB capacity. One 16-bit-wide
EEPROM module is needed to offer the 256-kB capacity.
The on-chip FLASH memory occupies the space from $C0000 to $FFFFF. The address space
from 0x00000 to 0xBFFFF is available for assignment. The following memory space assignment
will be appropriate for this project:
SRAM: $00000
,
$3FFFF
; 256 kB
EEPROM: $40000
,
$7FFFF
; 256 kB
PPI:
$BFFFC
,
$BFFFF
; 4 bytes
▲
The function of an address decoder is to make sure that no more than one memory device
is enabled to drive the data bus at a time. If there are two or more memory devices driving the
same bus lines,
bus contention
will occur and could cause severe damage to the system. All
memory devices or peripheral devices have control signals such as
chip enable
(CE),
chip select
(CS), or
output enable
(OE) to control their read and write operations. These signals are often
asserted low. The address decoder outputs will be used as the chip-select or chip-enable signals
of external memory devices.
Two address-decoding schemes have been used:
full decoding
and
partial decoding
. A
memory device is said to be
fully decoded
when each of its addressable locations responds to
only a single address on the system bus. A memory component is said to be
partially decoded
when each of its addressable locations responds to more than one address on the system bus.
Memory components such as DRAM, SRAM, EPROM, EEPROM, and flash memory chips use
the full address-decoding scheme more often, whereas peripheral chips or devices use the par-
tial address-decoding scheme more often.
Address decoder design is closely related to memory space assignment. For the address
space assignment made in Example 14.15, the higher address signals are used as inputs to the
decoder, and the lower address signals are applied to the address inputs of memory devices.
Before
programmable logic devices
(PLDs) became popular and inexpensive, designers used
transistor-transistor logic (TTL) chips such as the 74LS138 as address decoders. However, the
off-the-shelf TTL decoders force designers to use equal-size memory space assignment. When
PLDs became popular and inexpensive, designers started to use them to implement address de-
coders. PLDs allow the designer to implement demand assignment.
One of the methods for implementing the address decoder is to use one of the hardware
description languages (HDL), such as ABEL, CUPL, VHDL, or VERILOG. Low-density PLDs,
such as GAL18V10, GAL20V8, GAL20V8, SPLD16V8, SPLD20V8, and SPLD20V8, are often
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