Internal Memory Configuration and External Expansion - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 731

the address signals so that they stay valid throughout the bus cycle. In a microcontroller that
multiplexes the address and data buses, the address signals are placed on the multiplexed bus
first, along with certain control signals to indicate that the address signals are valid. After the
address signals are on the bus long enough so that the external logic has time to latch them,
the microcontroller stops driving the address signals and either waits for the memory devices to
place data on the multiplexed bus (in a read bus cycle) or places data on the multiplexed bus (in
a write bus cycle).

14.7.5 The HCS12 Bus Cycles
When adding external memory chips to the HCS12, it is important to make sure that all
the timing requirements of the MCU and memory chips are satisfied. The timing requirements
of the HCS12 are specified using a diagram as shown in Figure 14.32. The value for each timing
requirement is listed in Table 14.9. The interval when the ECLK signal is high can be stretched
by one to three minimum ECLK cycles ( t cyc ) to accommodate slower memory devices.

1, 2

3 4

ECLK

5

6 16 10

9 15 11

Addr/Data
(read)

Addr Data

8

7

13

12 14

Addr/Data
(write)

Addr Data

17 18

19

XA19:
XA14

20 21

22 23

ECS

24 25

26

R/W

27 28 29

LSTRB

30 31 32

NOACC

33 34 35 36

IPIPE0
IPIPE1

Figure 14.32 ■ The HCS12 read/write bus cycle timing diagram