Internal Memory Configuration and External Expansion - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 732

The timing diagram in Figure 14.32 does not clearly describe how a read bus cycle and a
write bus cycle proceed. A read bus cycle starts from the HCS12 driving the address signals onto
the address bus to select a location to read. The sequence of events that occurs when the HCS12
family MCU performs a read from an external memory is illustrated in Figure 14.33. In a read
bus cycle, the R/W signal stays high and the external memory drives the data onto the data bus.
A write cycle also starts with the HCS12 driving the address signals onto the address bus
to select a memory location to receive the data. The sequence of events that occurs when the
HCS12 family MCU performs a write access to the external memory is shown in Figure 14.34.
In a write bus cycle, the R/W signal goes low and the MCU drives the data onto the data bus.

Num Parameter Name Symbol Min Typ Max Unit

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

Frequency of operation (E-clock)
Cycle time
Pulse width, E low
Pulse width, E high
Address delay time
Address valid time to E rise ( PW EL 2 t AD )
Muxed address hold time
Address hold to data valid
Data hold to address
Read data setup time
Read data hold time
Write data delay time
Write data hold time
Write data setup time 1 ( PW EH 2 t DDW )
Address access time 1 ( t cyc 2 t AD 2 t DSR )
E high access time 1 ( PW EH 2 t DSR )
Nonmultiplexed address delay time
Nonmuxed address valid to E rise ( PW EL 2 t NAD )
Nonmultiplexed address hold time
Chip-select delay time
Chip-select access time 1 ( t cyc 2 t CSD 2 t DSR )
Chip-select hold time
Chip-select negated time
Read/write delay time
Read/write valid time to E rise ( PW EL 2 t RWD )
Read/write hold time
Low strobe delay time
Low strobe valid time to E rise ( PW EL 2 t LSD )
Low strobe hold time
NOACC strobe delay time
NOACC valid time to E rise ( P WEL - t NOD )
NOACC hold time
IPIPO[1:0] delay time
IPIPO[1:0] valid time to E rise ( PW EL 2 t P0D )
IPIPO[1:0] delay time 1 ( PW EL 2 t P1V )
IPIPO[1:0] valid time to E fall

f o
t cyc
PW EL
PW EH
t AD
t AV
t MAH
t AHDS
t DHA
t DSR
t DHR
t DDW
t DHW
t DSW
t ACCA
t ACCE
t NAD
t NAV
t NAH
t CSD
t ACCS
t CSH
t CSN
t RWD
t RWV
t RWH
t LSD
t LSV
t LSH
t NOD
t NOV
t NOH
t P0D
t P0V
t P1D
t P1V

0
40
19
19
-
11
2
7
2
13
0
-
2
12
19
6
-
15
2
-
11
2
8
-
14
2
-
14
2
-
14
2
2
11
2
11

-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

25.0
-
-
-
8
-
-
-
-
-
-
7
-
-
-
-
6
-
-
16
-
-
-
7
-
-
7
-
-
7
-
-
7
-
25
-

MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

1 Affected by clock stretch: add N 3 t cyc , where N = 0, 2, or 3, depending on the number of clock stretches.
Table 14.9 ■ HCS12 expanded bus timing characteristics