Hardware Reference
In-Depth Information
accommodate slower memory components. When data from external memory is not ready, the
control circuitry does not pull the Ready signal to low. When the Ready signal is sampled to be
low, the microcontroller copies the data into the CPU. The HCS12 microcontroller does not
use the Ready signal to accommodate slower memory. In a write bus cycle, the CPU sends both
the address and the data and requires no return of data.
In a bus transaction, there must be a device that can initiate a read or write transaction.
The device that can initiate a bus transaction is called a bus master . A microcontroller is al-
ways a bus master. A device such as a memory chip that cannot initiate a bus transaction is
called a bus slave .
In a bus transaction, there must be a signal to synchronize the data transfer. The signal
that is used most often is a clock signal. The bus is synchronous when a clock signal is used to
synchronize the data transfer. In a synchronous bus, the timing parameters of all signals use the
clock signal as the reference. As long as all timing requirements are satisfied, the bus transac-
tion will be successful. An asynchronous bus , on the other hand, is not clocked. Instead, self-
timed, handshaking protocols are used between the bus sender and receiver. Figure 14.31 shows
the steps of a master performing a read on an asynchronous bus. A synchronous bus is often
used between the CPU and the memory system, whereas an asynchronous bus is often used to
handle different types of I/O devices. A synchronous bus is usually faster because it avoids the
overhead of synchronizing the bus for each transaction.
Master asserts address
Address
Data
Slave drives data
Read
Request
ACK
Figure 14.31 Asynchronous read bus transaction
14.7.4 Bus Multiplexing
Designers of microcontrollers prefer to minimize the number of signal pins because it will
make the chip less expensive to manufacture and use. By multiplexing the address bus and the
data bus, many signal pins can be saved. The drawback of multiplexing bus signals is that the
achievable bus transaction performance is compromised. Most 8-bit and many 16-bit microcon-
trollers multiplex their address and data buses.
For any bus transaction, the address signal input to the memory chips must be stable
throughout the whole bus transaction. The memory system will need to use a circuit to latch
 
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