Internal Memory Configuration and External Expansion - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 726

Signal Name Function

ADDR0/DATA0
ADDR1/DATA1
ADDR2/DATA2
ADDT3/DATA3
ADDT4/DATA4
ADDT5/DATA5
ADDT6/DATA6
ADDT7/DATA7
ADDR8/DATA8
ADDR9/DATA9
ADDR10/DATA10
ADDT11/DATA11
ADDT12/DATA12
ADDT13/DATA13
ADDT14/DATA14
ADDT15/DATA15
XADDR14
XADDR15
XADDR16
XADDR17
XADDR18
XADDR19
R/W
LSTRB
ECLK
ECS/ROMONE
XCS

EMI address bit 0 or data bit 0
EMI address bit 1 or data bit 1
EMI address bit 2 or data bit 2
EMI address bit 3 or data bit 3
EMI address bit 4 or data bit 4
EMI address bit 5 or data bit 5
EMI address bit 6 or data bit 6
EMI address bit 7 or data bit 7
EMI address bit 8 or data bit 8
EMI address bit 9 or data bit 9
EMI address bit 10 or data bit 10
EMI address bit 11 or data bit 11
EMI address bit 12 or data bit 12
EMI address bit 13 or data bit 13
EMI address bit 14 or data bit 14
EMI address bit 15 or data bit 15
EMI extended address bit 14
EMI extended address bit 15
EMI extended address bit 16
EMI extended address bit 17
EMI extended address bit 18
EMI extended address bit 19
Read/write
Lower byte strobe
E-clock
Emulated chip select/on-chip ROM enable
External data chip select

Note: EMI stands for external memory interface

Table 14.7 ■ HCS12 external memory interface signal pins

XADDR19, . . . , XADDR14 are used as expanded address signals. In the following discussion, we
will use A0, . . . , A15, D0, . . . , D15, and XA14, . . . , XA19 to refer to ADDR0, . . . , ADDR15,
DATA0, . . . , DATA15, and XADDR14, . . . , XADDR19, respectively. The R/W signal is used to
indicate the direction of data transfer. When this signal is high, the MCU reads data from external
memory chips. When this signal is low, the MCU writes data to the external memory. The LSTRB
signal is used to indicate whether the lower data bus (DA7, . . . , DA0) carries valid data. There are
two situations in which the lower data bus does not carry valid data.
1. In expanded narrow mode, external memory data pins are connected to the D15, . . . ,
D8 pins. D7, . . . , D0 are not used to carry data.
2. In expanded wide mode, the MCU may execute instructions to write byte data to
memory locations at even addresses.
The signals LSTRB, R/ W, and A0 indicate the type of bus access that is taking place. Accesses
to the internal RAM module are the only type of access that would produce LSTRB 5 A0 5 1,
because the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single
cycle. In these cases, the data at the given address is on the lower half of the data bus, and the data
at address 1 1 is on the upper half of the data bus. These are summarized in Table 14.8.