Controller Area Network (CAN) - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 673

Step 2
Choose the CAN system-clock frequency (and hence set the CAN bus time quantum t Q ).
The CAN system clock will be the CPU oscillator output or the E-clock divided by a prescale
factor. The CAN system clock is chosen so that the desired CAN bus nominal bit time ( t NBT )
is an integer multiple of time quanta (CAN system-clock period) from 8 to 25.
Step 3
Calculate prop_seg duration. The number of time quanta required for the prop_seg can
be calculated by using Equation 13.5. If the result is greater than 8, go back to step 2 and
choose a lower CAN system-clock frequency.
Step 4
Determine phase_seg1 and phase_seg2 . Subtract the prop_seg value and 1 (for sync_seg ) from
the time quanta contained in a bit time. If the difference is less than 3, then go back to step
2 and select a higher CAN system-clock frequency. If the difference is an odd number greater
than 3, then add 1 to the prop_seg value and recalculate. If the difference is equal to 3, then
phase_seg1 5 1 and phase_seg2 5 2 and only one sample per bit may be chosen. Otherwise,
divide the remaining number by 2 and assign the result to phase_seg1 and phase_seg2 .
Step 5
Determine the resynchronization jump width (RJW). RJW is the smaller of 4 and phase_seg1 .
Step 6
Calculate the required oscillator tolerance from Equations 13.6 and 13.7. If phase_seg1 . 4,
it is recommended to repeat steps 2 to 6 with a larger value for the prescaler. Conversely,
if phase_seg1 , 4, it is recommended to repeat step 2 to 6 with a smaller value for the
prescaler, as long as prop_seg , 8, as this may result in a reduced oscillator tolerance
requirement. If the prescaler is already equal to 1 and a reduced oscillator tolerance is still
required, the only option is to consider using a clock source with higher frequency.

Example 13.1
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Calculate the CAN bit segments for the following system constraints:
Bit rate 5 100 kbps
Bus length 5 25 m
Bus propagation delay 5 5 3 10 29 s/m
MCP2551 transceiver plus receiver propagation delay 5 150 ns at 85°C
CPU oscillator frequency 5 8 MHz
Solution: Let's follow the procedure described earlier.
Step 1
Physical delay of bus 5 125 ns
t PROP_SEG 5 2 3 (125 ns 1 150 ns) 5 550 ns
Step 2
Try the prescaler of 4 for the CAN system clock of 8 MHz, which gives a time quantum of
500 ns. One bit time is 10

μ s. This gives 10,000/500 5 20 time quanta per bit.

Step 3
Prop_seg 5 round_up (550 ns 4 500 ns) 5 round_up (1.1) 5 2. Phase_seg1 1 phase_seg2
5 20 2 1 2 prop_seg 5 17 . 16.
Set prescaler to 8. Then one time quantum is 1 µs and one bit time has 10 time quanta.
The new prop_seg 5 round_up (550 ns 4 1000 ns) 5 1.