Controller Area Network (CAN) - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 672

where t PROP(A, B) and t PROP(B, A) are the propagation delays from node A to B and node B to node A,
respectively. In the worst case, node A and node B are at the two ends of the CAN bus. The
propagation delay from node A to node B is given by
t PROP(A, B) 5 t BUS 1 t Tx 1 t Rx (13.3)
where t BUS , t T x , and t R x are data traveling time on the bus, transmitter propagation delay, and
receiver propagation delay, respectively.
Let node A and node B be two nodes at opposite ends of the CAN bus, then the worst-case
value for t PROP_SEG is
t PROP_SEG 5 2 3 ( t BUS 1 t Tx 1 t Rx ) (13.4)
The minimum number of time quanta ( t Q ) that must be allocated to the prop_seg segment is
therefore
prop_seg 5 round_up ( t PROP_SEG 4 t Q ) (13.5)
where the round_up () function returns a value that equals the argument rounded up to the next
integer value.
In the absence of bus errors, bit stuffing guarantees a maximum of 10 bit periods between
resynchronization edges (5 dominant bits followed by 5 recessive bits and then followed by a
dominant bit). This represents the worst-case condition for the accumulation of phase error dur-
ing normal communication. The accumulated phase error must be compensated for by resyn-
chronization and therefore must be less than the programmed resynchronization jump width
( t RJW ). The accumulated phase error is due to the tolerance in the CAN system clock, and this
requirement can be expressed as
(2 3 Δ f ) 3 10 3 t NBT , t RJW (13.6)
where D f is the largest crystal oscillator frequency variation (in percentage) of all CAN nodes in
the network.
Real systems must operate in the presence of electrical noise, which may induce errors on the
CAN bus. A node transmits an error flag after it detects an error. In the case of a local error, only
the node that detects the error will transmit the error flag. All other nodes receive the error flag
and transmit their own error flags as an echo. If the error is global, all nodes will detect it within
the same bit time and will therefore transmit error flags simultaneously. A node can therefore dif-
ferentiate between a local error and a global error by detecting whether there is an echo after its er-
ror flag. This requires that a node can correctly sample the first bit after transmitting its error flag.
An error flag from an error-active node consists of 6 dominant bits, and there could be up
to 6 dominant bits before the error flag, if, for example, the error was a stuff error. A node must
therefore correctly sample the 13th bit after the last resynchronization. This can be expressed as

(2 3 Δ f ) 3 (13 3 t NBT 2 t PHASE_SEG2 ) , MIN ( t PHASE_SEG1 , t PHASE_SEG2 ) (13.7)

where the function MIN(arg1,arg2) returns the smaller of the two arguments.
Thus there are two clock tolerance requirements that must be satisfied. The selection of bit
timing values involves consideration of various fundamental system parameters. The require-
ment of the prop_seg value imposes a trade-off between the maximum achievable bit rate and
the maximum propagation delay, due to the bus length and the characteristics of the bus driver
circuit. The highest bit rate can only be achieved with a short bus length, a fast bus driver cir-
cuit, and a high-frequency CAN clock source with high tolerance.
The procedure for determining the optimum bit timing parameters that satisfy the require-
ments for proper bit sampling is as follows:
Step 1
Determine the minimum permissible time ( t PROP_SEG ) for the prop_seg segment using
Equation 13.4.