Controller Area Network (CAN) - The HCS12/9S12: An Introduction to Software and Hardware Interfacing - page 674

Step 4
Subtracting 1 for prop_seg and 1 for sync_seg from 10 time quanta per bit gives 8. Since the
result is equal to 8 and is even, divide it by 2 (quotient is 4) and assign it to phase_seg1 and
phase_seg2.
Step 5
RJW is the smaller one of 4 and phase_seg1 and is 4.
Step 6
From Equation 13.6,
Δ f , RJW 4 (20 3 NBT) 5 4 4 (20 3 10) 5 2.0 percent
From Equation 13.7,
D f , MIN (phase_seg1, phase_seg2) 4 2(13 3 NBT 2 phase_seg2) 5 4 4 252 5 1.59 percent
The desired oscillator tolerance is the smaller of these values, 1.59 percent.
In summary,
Prescaler

5 8

Nominal bit time 5 10

prop_seg 5 1

sync_seg 5 1

phase_seg1 5 4

phase_seg2 5 4

RJW 5 4

Oscillator tolerance 5 1.59 percent

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Example 13.2
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Calculate the bit segments for the following system constraints:
Bit rate 5 500 kbps
Bus length 5 50 m
Bus propagation delay 5 5 3 10 29 s/m
MCP2551 transmitter plus receiver propagation delay 5 150 ns at 85°C
CPU oscillator frequency 5 E-clock frequency 5 16 MHz
Solution: Follow the standard procedure to perform the calculation.
Step 1
Physical delay of bus 5 250 ns
t PROP_SEG 5 2 3 (250 ns 1 150 ns) 5 800 ns
Step 2
A prescaler of 2 for a CAN system clock of 16 MHz gives a time quantum of 125 ns. The
nominal bit time is 2 μ s. This gives 2000/125 5 16 time quanta per bit.

Step 3
Prop_seg 5 round_up (800 ns 4 125 ns) 5 round_up (6.4) 5 7.