Hardware Reference
In-Depth Information
7
6
5
4
3
2
1
0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN
x
IDMR4
Reset:
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN
x
IDMR5
Reset:
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN
x
IDMR6
Reset:
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
CAN
x
IDMR7
Reset:
0
0
0
0
0
0
0
0
Figure 13.32
■
MSCAN identifier mask registers (second bank) (
x
5
0, 1, 2, 3, or 4)
Address
Register Name
$_x0
$_x1
$_x2
$_x3
$_x4
$_x5
$_x6
$_x7
$_x8
$_x9
$_xA
$_xB
$_xC
$_xD
$_xE
$_xF
Identifier register 0
Identifier register 1
Identifier register 2
Identifier register 3
Data segment register 0
Data segment register 1
Data segment register 2
Data segment register 3
Data segment register 4
Data segment register 5
Data segment register 6
Data segment register 7
Data length register
Transmit buffer priority register
1
Time stamp register high byte
2
Time stamp register low byte
2
1
Not applicable for receive buffer.
2
Read-only for CPU.
Figure 13.33
■
MSCAN message buffer organization
I
DENTIFIER
R
EGISTERS
(IDR0
=
IDR3)
All four identifier registers are compared when a message with an extended identi-
fier is received. The contents of these four identifier registers are shown in Figure 13.34.
When a message with the standard identifier is received, only the first two identifier reg-
isters are compared. The meaning of the standard identifier is illustrated in Figure 13.35.
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