Hardware Reference
In-Depth Information
MSCAN R
ECEIVE
E
RROR
C
OUNTER
R
EGISTER
(CAN
X
RXERR)
This register reflects the status of the MSCAN receive error counter. This register can be
read only in sleep or initialization mode. Reading this register in any other mode may return an
incorrect value.
MSCAN T
RANSMIT
E
RROR
C
OUNTER
R
EGISTER
(CAN
X
TXERR)
This register reflects the status of the MSCAN transmit error counter. Like CAN
x
RXERR,
this register can be read correctly only in sleep or initialization mode.
MSCAN I
DENTIFIER
A
CCEPTANCE
R
EGISTERS
(CAN
X
IDAR0
=
7)
On reception, each message is written into the background receive buffer. The CPU is only
signaled to read the message if it passes the criteria in the identifier acceptance and identifier
mask registers (accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDAR0 to IDAR3 registers of the
incoming messages in a bit-by-bit manner. For extended identifiers, all four acceptance and mask
registers are applied. For standard identifiers, only the first two are applied. The contents of the
first bank and second bank acceptance registers are shown in Figures 13.29 and 13.30, respectively.
The actual application of acceptance and mask registers is controlled by the CAN
x
IDAC register.
AC7,AC0 comprise a user-defined sequence of bits with which the corresponding bits of the
related identifier register (IDR
n
) of the receive message buffer are compared. The result of this com-
parison is then masked with the corresponding identifier mask register to determine if there is a hit.
MSCAN I
DENTIFIER
M
ASK
R
EGISTERS
(CAN
X
IDMR0
=
7)
The identifier mask registers specify which of the corresponding bits in the identifier
acceptance register are relevant for acceptance filtering. The contents of the first and second
banks of the identifier mask registers are shown in Figures 13.31 and 13.32, respectively. If a
mask bit is 1, its corresponding acceptance bit will be ignored.
7
6
5
4
3
2
1
0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN
x
IDAR0
Reset:
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
AC7
AC5
AC1
CAN
x
IDAR1
AC6
AC4
AC3
AC2
AC0
Reset:
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN
x
IDAR2
Reset:
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
CAN
x
IDAR3
Reset:
0
0
0
0
0
0
0
0
Figure 13.29
■
MSCAN identifier acceptance registers (first bank) (
x
5
0, 1, 2, 3, or 4)
Search WWH ::
Custom Search